VLSI Core - IC Design Technology Experts

Mentor Graphics User2User Conference 2011 - Bangalore - 02 Dec 2011

2011-10-28T22:19:00.000-07:00

User2User 2011 India

You are invited toUser2User India 2011, the International Mentor Graphics user conference to be held on December 02, 2011 in Bangalore, India.
Join us for a full day of technical sessions and gain immediately-useful knowledge in areas including Functional Verification, Silicon Test, Design 2 Silicon and System Design. Meet technical experts from user group of Mentor Graphics, Mentor technical staff and see product demos, learn best practices from other Mentor customers, and network with your colleagues. It all happens on:

Date: December 02, 2011
Location: Vivanta by Taj on MG Road (formerly Taj Residency), Bangalore
41/3 Mahatma Gandi Road
Bangalore 560001

Don't miss out on this excellent networking and learning opportunity.

Register today!

Registration ends on 30 Nov, 2011

IC Design EDA Tools & Software

2011-09-27T23:20:00.000-07:00

EDA Tools & Software collection

Thanks for your interest. Feel free to add the EDA tools/softwares for IC Design/FPGA that you are aware of.
Visit the EDA Tools collection page here.

Added EDA Tools/Software will be reviewed & updated to a new page soon.
Thanks for your help to keep this list up to date.

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Cypress-ARM: CORTEX-M3 PSoC 5 Design Challenge

2011-01-19T01:34:00.001-08:00

Join the ARM-PSoC Design Challenge With $10,000 in Cash and Prizes

Deadline extended to January 24^th.

Want to put your ARM and PSoC design skills up against those of your peers?

Want to present your design directly to Cypress CEO T.J. Rodgers and Cypress’s executive staff?

Want to comment on your peers’ PSoC designs, holding power over whether their designs get time
in the industry spotlight from Cypress and EE Times?

Check out the ARM® Cortex™M3/PSoC 5 Design Challenge, a test of design skill geared to determine the
most innovative and useful designs for the Cypress PSoC 5 architecture. The PSoC 5 solution is powered by
the ARM Cortex-M3 processor.

Prizes awarded for top designs, best video and community choice as well as community members who
participate in the forums or provide ratings on design entries.

Visit www.cypress.com/go/challenge now to check out the contest and enter your design.

Source: Cypress Newsletter

EDA Tech Forum - 2010 - Bangalore & New Delhi (India)

2010-07-28T23:14:00.000-07:00

EDA TECH FORUM INDIA
Delivering the Latest in 10X Design Improvements

Two Locations:
Bangalore- Wednesday, August 18, 2010
New Deli - Friday, August 20, 2010
8:00 – 17:50

Join other EE designers and engineers at one of two complimentary EDA Tech Forums in India - Bangalore and New Delhi. This year's event series features a new lineup of speakers, sponsors, and technology tracks in a one-day event that provides an excellent mix of educational and networking opportunities.

Create your personal agenda with tracks in:

Maximizing Front-end Design: From ESL through RTL
Accelerate Time to Manufacturing
Increase Productivity in System-level Design
Innovations in Embedded Software and User Interface Development

Start the day with exciting keynote speakers, like Pamela Kumar of IBM, Manjunath Hebbar of HCL Technologies, and Pravin Madhani of Mentor Graphics as he discusses how in the next five years, 10X improvements in design methodologies are needed. After attending in-depth technical breakout sessions, there will also be plenty of time to meet with leading EDA solution providers in the multi-vendor fair.

Event Highlights:

Attend in-depth technical sessions from sponsors
Test drive new tools from EDA solution providers at the multi-vendor fair
Enjoy great food and win prizes while you network with fellow EE designers

Guarantee your participation at the EDA Tech Forum. Register today.

Gary Smith EDA market statistics 2010: Summary

2010-07-23T03:20:00.000-07:00

Gary Smith EDA market statistics 2010: Summary

(July 22, 2010) -- These market statistics were compiled by Nancy Wu & Mary Olsson, part of the Gary Smith EDA team. The biggest change in 2009 was Mentor passing Cadence to become number two in product sales in EDA. This is an indication of the market shift caused by the move into the ESL Methodology. Synopsys remains a strong number one.

Mentor also grabbed #2 overall in IC design. With the acquisition of Valor, Mentor is also now 3× as large as its next competitor in PCB design.

We believe that the recent changes in Cadence has stopped their market share decline, similar to the changes made at Mentor, bringing in Walden Rhines, during the switch to the RTL design methodology.

Read more to know the statistics report - Click Here

Source: This article is from Solid State Technology

ESC Silicon Valley - San Jose, CA (April 26-29, 2010)

2010-03-11T23:09:00.000-08:00

More info. & Register : http://bit.ly/esc4sj

ESC Silicon Valley - San Jose, CA (April 26-29, 2010)

Attend the next ESC which brings together system architects, design engineers, suppliers, analysts and media from across the globe. With 10,000 total attendees, it’s the largest and most prestigious annual engineering event in America. Participate in ESC, and you will meet with your customers, renew relationships, sell to pro...spects, attend press meetings, make announcements, and talk to partners – Only at ESC.

Keynote Speakers:

Dr. Michio Kaku
Theoretical Physicist, Bestselling Author and Science Popularizer

Richard Templeton
Chairman, President, Chief Executive Officer, Texas Instruments

Jason Wolf
Vice President, North America, Better Place

More info. & Register : http://bit.ly/esc4s

How to Search & Replace in 2GB Big Text File?

2010-03-10T00:56:00.000-08:00

Problem Statement:

I am trying to edit few lines in a file, but it is a very big file more than 2GB text file. Opening, editing and saving in vi editor takes a long time.

1. To search and replace a string 'STRING' in a big file.

2. To find few lines having string 'GROUPS' and remove them from the original file.I tried 'grep -v 'GROUPS' file > newfile', is there any better way than this.

Is this possible to do without opening a file through other ways not in Vi editor.

Perl Solution
    perl  -e 's/gopher/World Wide Web/gi'  -p  -i.bak  *.html
This command, issued at the Unix prompt, executes the short Perl program specified in single quotes. This program consists of one Perl operation: it substitutes for original word "gopher" the phrase "World Wide Web" (globally, ignoring case). The command line options imply that the Perl program should run for each file ending in .html in the current directory. If any file blah.html needs changing, a backup of the original is made as file blah.html.bak.�

For more info on perl, please go through
http://www.cs.tut.fi/~jkorpela/perl/course.html#whatis

sed solution:
for deleting GROUPS from all lines
use this :
sed -i '/GROUPS/d' file_name
OR
sed 's/old_string/new_string/g' oldfilename > newfilename

Source: VLSICore Members

3D Field Solvers can be Fast - Daniel Payne

2009-12-10T02:33:00.000-08:00

3D Field Solvers can be Fast
by Daniel Payne in Extraction tools

In SoC designs today parasitic extraction tools produce RC and sometimes L or S-parameter values for full-chip designs using either pattern-matching or equation-based techniques. It gets the job done for most digital designs however when you really need accuracy in your parasitics then you must consider something more accurate, namely a 3D field solver.

23rd International VLSI Conference (2010) - January 3-7, 2010 - Bangalore India

2009-11-21T10:31:00.000-08:00

This joint conference is a forum for researchers and designers to present and discuss various aspects of VLSI design, electronic design automation (EDA), enabling technologies, and embedded systems. It covers the entire spectrum of activities in the two vital areas of very large scale integration (VLSI) and embedded systems, which underpin the semiconductor industry. The five-day technical program will consist of three days of regular paper sessions, special sessions, embedded tutorials, industry presentation sessions, panel discussions, design contests and industrial exhibits, and two days of full-day tutorials.

Electronic systems are ubiquitous today in multiple applications, with emerging markets in health-care, entertainment and machine intelligence spurring several new ones. These markets often hinge delicately on the right blend of technology and affordability. Accordingly, the theme for this conference is set as “Affordable Technology for Emerging Markets”.

Tutorials	Conference
Day 1: Sunday January 3, 2010	Day 1: Tuesday January 5, 2010
Day 2: Monday January 4, 2010	Day 2: Wednesday January 6, 2010
	Day 3: Thursday January 7, 2010

IMPORTANT DATES
Fellowship Notification	:	Nov. 16^th, 2009
Registration (Early bird rates)	:	Dec. 7^th, 2009
Exhibits (Early bird rates)	:	Dec. 7^th, 2009

Links: http://vlsiconference.com/vlsi2010/

DipTrace - Advanced PCB Layout Software

2009-11-18T10:47:00.000-08:00

DipTrace Free – 1.30

DipTrace is an advanced PCB design software application that consists of 4 modules: PCB Layout with efficient auto-router, Schematic Capture, Component and Pattern Editors that allow you to design your own component libraries. Besides being very simple to learn, which is quite an accomplishment for a PCB design software package, this solution has a very intuitive user interface and many innovative features. For instance, a schematic can be converted to a PCB with one mouse click. The board designer can instantly renew the PCB from an updated version of schematic and keep existing placement, routed traces, board outline, mounting holes and other work. PCB and Schematic can be compared at any design stage to ensure they are identical. DipTrace has a powerful automatic router, superior to many routers included in other PCB layout packages. It can route a single layer and multilayer circuit boards, and there is an option to autoroute a single layer board with jumper wires, if required.

DipTrace also provides you with external autorouter support. Smart manual routing tools allow users to finalize the design and to get the results they want in a blink of an eye. Accurate shape-based copper pour system with different possible fill types and thermals can be used to make planes or to reduce manufacturing costs. Other important features are Electrical Rule Check (ERC), Design Rule Check (DRC) and Net Connectivity Check – the functions that check connections in Schematic by different rules (pin type, short circuit, etc.), the clearance between layout objects, which ensures board accuracy, and connectivity of all nets not depending on how they are connected (with traces, thermals or shapes). DipTrace modules allow you to exchange schematics, layouts and libraries with other EDA and CAD packages. DipTrace Schematic Capture and PCB Layout also support popular netlist formats. Output formats are DXF, Gerber, Drill and G-code. Standard libraries include 50.000+ components.

DipFree Download here

Try DipTrace and you will be surprised! DipTrace is a complete state-of-the-art PCB Design System. It includes:

PCB Layout — PCB design with an easy to use manual routing tools, auto-router and auto-placer.
Schematic — Schematic Capture and export to PCB or Spice.
Pattern Editor — allows you to create part footprints.
Component Editor — allows you to draw parts and make components.

Watch DipTrace in action!

Get 250-pin Freeware now!


Schematic Capture	PCB Layout

DipTrace provides the following features:

Easy to learn user interface
To design a schematic, simply select and place components onto your document and connect them together using the wire and bus tools. Multisheet design is supported. Then select the menu option 'Convert to PCB' to convert the schematic to PCB. Layout can be updated from Schematic in a few clicks at anytime. When you create or edit design objects they are highlighted to improve your work. Step-by-step tutorial available from web-site guides you through the design process and allows to get started with ease.

Smart placement and auto-placement features
After converting Schematic to PCB layout, place board outline and arrange components. Then use "placement by list" for chips/connectors and auto-placement for other components to get acceptable result in a few minutes and start routing.

Easy to use manual and powerful automatic routing
DipTrace PCB software includes an advanced grid-based automatic router that is able to route single-layer and multi-layer boards. It is available with a 'rip-up and retry' algorithm. With Specctra DSN/SES interface you can use external shape-based or topological autorouter. Intelligent manual routing tools allow you to create and edit traces by 90, 45 degree or without any limitations. Curved traces are supported. Through, blind or buried vias can be used in automatic and manual routing. Board size is not limited.

Shape-based copper pour
Powerful copper pour system can help to reduce your manufacturing costs by minimizing the amount of etching solution required. To use it, all you have to do is insert a copper area on your board in the PCB Layout program and any pad or trace inside the selected area will be automatically surrounded with a gap of the desired size. Using copper pour you can also create planes and connect them to pads and vias (different thermal types are supported).

Advanced Verification Features
Schematic and PCB design modules have number of verification features that help control project accuracy on different design stages: The ERC function shows possible errors in Schematic pin connections using defined rules and allows you to correct errors step-by-step. DRC function checks the clearance between design objects, minimum size of traces, and drills. Errors are displayed graphically and you can fix them step-by-step and rerun the DRC in one click after any corrections. Net Connectivity Check verifies if all nets of PCB are electrically connected. This feature uses traces, copper pour filled area and shapes to control connectivity, then reports broken and merged nets with area details. Comparing to Schematic allows you to check if routed PCB is identical with Schematic.

Spice Support
Using DipTrace Schematic or Component Editor specify spice settings or attach models to the components. Then export .cir net-list of your Schematic to LT Spice or another simulation software to verify how it works.

Import/Export Features
Package modules allow you to exchange schematics, layouts and libraries with other EDA and CAD packages. DipTrace Schematic Capture and PCB Layout also support Accel, Allegro, Mentor, PADS, P-CAD, Protel and Tango netlist formats.

Manufacturing output formats
DipTrace provides support for a number of different manufacturing output formats. Using this PCB software you can produce N/C Drill files for numerically controlled (N.C.) drilling machines and RS-274X Gerber files for sending to board manufacturers. Vectorizing function allows to export true-type fonts and raster images. Also DipTrace supports DXF output.

Producing PCBs using milling method
DipTrace allows you to export edge polylines to DXF. The DXF files can be converted to G-code with Ace Converter (it's free). Before edge exporting the DRC function of pcb layout program checks the design and shows possible problems if exist.

Standard component libraries
DipTrace package includes component and pattern libraries which contain 90,000+ components from different manufacturers.

Creation of your own libraries
Component and Pattern Editors allow to design your own symbols and patterns. To create complete components simply connect them together using Component Editor.

... and much more!

Mentor Graphics: User2User India (U2U) - 04 December 2009, Bangalore

2009-11-10T10:15:00.000-08:00

USER2USER 2009

User2User India 2009
December 4
Taj Residency, Bangalore

You are invited to User2User India 2009, the Mentor Graphics user conference to be held on Friday, December 4 in Bangalore, India.

Join us for a full day of technical sessions and gain immediately-useful knowledge in areas including System Design, Functional Verification & Emulation, Design 2 Silicon, Silicon Test and CFD.

Keynote Speakers

Wesley Ryder, Worldwide Technical Director, Mentor Graphics

Vamsi Boppana, Xilinx Inc

Pravin Desale, LSI Technologies (India) Pvt Ltd

Event Highlights

User will present case studies and best practices on how they address their most pressing design challenges

Get great insights on new techniques and methodologies used for leading challenges

Learn the latest advancements and usage experience from users

Great opportunity to meet other professionals like yourself and exchange expertise, tips and tricks, or industry happenings

Enjoy great food and win prizes while you network with fellow EE designers

Registration ends on 30 November, 2009.

LEARN MORE

REGISTER TODAY >>>

Apache Design Solutions Acquires Sequence Design

2009-09-08T23:30:00.001-07:00

Apache Design Solutions Acquires Sequence Design

Acquisition Expands Company’s Technology Leadership in Power and Noise Solutions to RTL Designs

San Jose, California – September 8, 2009 – Apache Design Solutions, the technology leader in power and noise integrity for Chip-Package-Systems (CPS) convergence, today announced it has acquired the assets, including intellectual property, and foreign subsidiaries of Sequence Design, the EDA leader in RTL Design for Power (DFP)™ solution. Sequence operations will be integrated under Apache’s global research and development, sales, support and marketing functions. Vic Kulkarni, President and CEO of Sequence Design, will assume the role of Senior Vice President and General Manager of RTL Business Unit in Apache. Terms of the transaction were not disclosed.

Through this acquisition, Apache expands power and noise product offerings from SoC, analog/mixed-signal, and package/PCB designs to the RTL where greater opportunity for power optimizations can be realized. The combination of Sequence’s technology and Apache’s power sign-off platforms raises the power-based solutions to the same level of importance as area and timing based tools.

“Sequence Design has established a solid reputation and customer base in RTL power analysis and reduction,” said Andrew Yang, CEO of Apache, “This acquisition reinforces Apache’s business and product strategy for complete offering of advanced power and noise integrity solutions for chip-package-system convergence.”

“Apache has demonstrated an impressive growth in the marketplace and established a critical mass of customer base, financial strength, and management experience. Our team looks forward to contributing to its continued success,” said Vic Kulkarni, President and CEO of Sequence.

Sequence Products:

PowerTheater, PowerArtist, Cool Products and Columbus will continue to be supported by Apache.

Apache Design SolutionsCPM, NSPICE, RedHawk, PakSI-E, PsiWinder, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc

Source:
http://www.apache-da.com/apache-da/Home/NewsandEvents/PressReleases/09.08.09.html
http://www.reuters.com/article/pressRelease/idUS225568+08-Sep-2009+BW20090908
http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=219700024

100 Keyboard Shortcuts

2009-07-29T02:53:00.000-07:00

General

CTRL+C (Copy)
CTRL+X (Cut)
CTRL+V (Paste)
CTRL+Z (Undo)
DELETE (Delete)
SHIFT+DELETE (Delete the selected item permanently without placing the item in the Recycle Bin)
CTRL while dragging an item (Copy the selected item)
CTRL+SHIFT while dragging an item (Create a shortcut to the selected item)
F2 key (Rename the selected item)
CTRL+RIGHT ARROW (Move the insertion point to the beginning of the next word)
CTRL+LEFT ARROW (Move the insertion point to the beginning of the previous word)
CTRL+DOWN ARROW (Move the insertion point to the beginning of the next paragraph)
CTRL+UP ARROW (Move the insertion point to the beginning of the previous paragraph)
CTRL+SHIFT with any of the arrow keys (Highlight a block of text)
SHIFT with any of the arrow keys (Select more than one item in a window or on the desktop, or select text in a document)
CTRL+A (Select all)
F3 key (Search for a file or a folder)

ALT+ENTER (View the properties for the selected item)
ALT+F4 (Close the active item, or quit the active program)
ALT+ENTER (Display the properties of the selected object)
ALT+SPACEBAR (Open the shortcut menu for the active window)
CTRL+F4 (Close the active document in programs that enable you to have multiple documents open simultaneously)
ALT+TAB (Switch between the open items)
ALT+ESC (Cycle through items in the order that they had been opened)
F6 key (Cycle through the screen elements in a window or on the desktop)
F4 key (Display the Address bar list in My Computer or Windows Explorer)
SHIFT+F10 (Display the shortcut menu for the selected item)
ALT+SPACEBAR (Display the System menu for the active window)
CTRL+ESC (Display the Start menu)
ALT+Underlined letter in a menu name (Display the corresponding menu)
Underlined letter in a command name on an open menu (Perform the corresponding command)
F10 key (Activate the menu bar in the active program)
RIGHT ARROW (Open the next menu to the right, or open a submenu)
LEFT ARROW (Open the next menu to the left, or close a submenu)
F5 key (Update the active window)
BACKSPACE (View the folder one level up in My Computer or Windows Explorer)
ESC (Cancel the current task)
SHIFT when you insert a CD-ROM into the CD-ROM drive (Prevent the CD-ROM from automatically playing)

Dialog Box Keyboard Shortcuts
CTRL+TAB (Move forward through the tabs)
CTRL+SHIFT+TAB (Move backward through the tabs)
TAB (Move forward through the options)
SHIFT+TAB (Move backward through the options)
ALT+Underlined letter (Perform the corresponding command or select the corresponding option)
ENTER (Perform the command for the active option or button)
SPACEBAR (Select or clear the check box if the active option is a check box)
Arrow keys (Select a button if the active option is a group of option buttons)
F1 key (Display Help)
F4 key (Display the items in the active list)
BACKSPACE (Open a folder one level up if a folder is selected in the Save As or Open dialog box)

m*cro$oft Natural Keyboard Shortcuts
Windows Logo (Display or hide the Start menu)
Windows Logo+BREAK (Display the System Properties dialog box)
Windows Logo+D (Display the desktop)
Windows Logo+M (Minimize all of the windows)
Windows Logo+SHIFT+M (Restore the minimized windows)
Windows Logo+E (Open My Computer)
Windows Logo+F (Search for a file or a folder)
CTRL+Windows Logo+F (Search for computers)
Windows Logo+F1 (Display Windows Help)
Windows Logo+ L (Lock the keyboard)
Windows Logo+R (Open the Run dialog box)
Windows Logo+U (Open Utility Manager)

Accessibility Keyboard Shortcuts
Right SHIFT for eight seconds (Switch FilterKeys either on or off)
Left ALT+left SHIFT+PRINT SCREEN (Switch High Contrast either on or off)
Left ALT+left SHIFT+NUM LOCK (Switch the MouseKeys either on or off)
SHIFT five times (Switch the StickyKeys either on or off)
NUM LOCK for five seconds (Switch the ToggleKeys either on or off)
Windows Logo +U (Open Utility Manager)
Windows Explorer Keyboard Shortcuts
END (Display the bottom of the active window)
HOME (Display the top of the active window)
NUM LOCK+Asterisk sign (*) (Display all of the subfolders that are under the selected folder)
NUM LOCK+Plus sign (+) (Display the contents of the selected folder)
NUM LOCK+Minus sign (-) (Collapse the selected folder)
LEFT ARROW (Collapse the current selection if it is expanded, or select the parent folder)
RIGHT ARROW (Display the current selection if it is collapsed, or select the first subfolder)

Shortcut Keys for Character Map
After you double-click a character on the grid of characters, you can move through the grid by using the keyboard shortcuts:
RIGHT ARROW (Move to the right or to the beginning of the next line)
LEFT ARROW (Move to the left or to the end of the previous line)
UP ARROW (Move up one row)
DOWN ARROW (Move down one row)
PAGE UP (Move up one screen at a time)
PAGE DOWN (Move down one screen at a time)
HOME (Move to the beginning of the line)
END (Move to the end of the line)
CTRL+HOME (Move to the first character)
CTRL+END (Move to the last character)
SPACEBAR (Switch between Enlarged and Normal mode when a character is selected)

m*cro$oft Management Console (MMC) Main Window Keyboard Shortcuts
CTRL+O (Open a saved console)
CTRL+N (Open a new console)
CTRL+S (Save the open console)
CTRL+M (Add or remove a console item)
CTRL+W (Open a new window)
F5 key (Update the content of all console windows)
ALT+SPACEBAR (Display the MMC window menu)
ALT+F4 (Close the console)
ALT+A (Display the Action menu)
ALT+V (Display the View menu)
ALT+F (Display the File menu)
ALT+O (Display the Favorites menu)
MMC Console Window Keyboard Shortcuts
CTRL+P (Print the current page or active pane)
ALT+Minus sign (-) (Display the window menu for the active console window)
SHIFT+F10 (Display the Action shortcut menu for the selected item)
F1 key (Open the Help topic, if any, for the selected item)
F5 key (Update the content of all console windows)
CTRL+F10 (Maximize the active console window)
CTRL+F5 (Restore the active console window)
ALT+ENTER (Display the Properties dialog box, if any, for the selected item)
F2 key (Rename the selected item)
CTRL+F4 (Close the active console window. When a console has only one console window, this shortcut closes the console)

Remote Desktop Connection Navigation
CTRL+ALT+END (Open the m*cro$oft Windows NT Security dialog box)
ALT+PAGE UP (Switch between programs from left to right)
ALT+PAGE DOWN (Switch between programs from right to left)
ALT+INSERT (Cycle through the programs in most recently used order)
ALT+HOME (Display the Start menu)
CTRL+ALT+BREAK (Switch the client computer between a window and a full screen)
ALT+DELETE (Display the Windows menu)
CTRL+ALT+Minus sign (-) (Place a snapshot of the active window in the client on the Terminal server clipboard and provide the same functionality as pressing PRINT SCREEN on a local computer.)
CTRL+ALT+Plus sign (+) (Place a snapshot of the entire client window area on the Terminal server clipboard and provide the same functionality as pressing ALT+PRINT SCREEN on a local computer.)

m*cro$oft Internet Explorer Navigation
CTRL+B (Open the Organize Favorites dialog box)
CTRL+E (Open the Search bar)
CTRL+F (Start the Find utility)
CTRL+H (Open the History bar)
CTRL+I (Open the Favorites bar)
CTRL+L (Open the Open dialog box)
CTRL+N (Start another instance of the browser with the same Web address)
CTRL+O (Open the Open dialog box, the same as CTRL+L)
CTRL+P (Open the Print dialog box)
CTRL+R (Update the current Web page)
CTRL+W (Close the current window)

IEEE 1801: UPF achieves formal standardisation as IEEE-1801

2009-07-23T04:39:00.000-07:00

The IEEE and the EDA-industry alliance Accellera
Shrenik Mehta, chairman of Accellera observes, "Industry acceptance of the IEEE 1801 standard power format can help optimize the energy consumption of future electronic systems by enabling engineers and tools to characterize and improve semiconductor power usage much earlier in the design cycle." announced today that the IEEE has approved a new standard, IEEE 1801, "Standard for Design and Verification of Low Power Integrated Circuits." The standard is also known as Unified Power Format (UPF) 2.0, and engineers in many chip-design teams worldwide already employ it to convey aspects of an IC design that are critical to low-power specifications from one tool to another throughout an electronic system design, analysis, verification and implementation flow.

EDA Blog: The IEEE has approved a new IEEE 1801 standard for Design and Verification of Low Power Integrated Circuits. The standard is also known as Unified Power Format (UPF) 2.0. UPF (first developed by Accellera) and is currently supported by multiple vendors and is in use worldwide. This is the first time that UPF has undergone an IEEE standardization effort. The IEEE 1801 standard provides portability of low-power design specifications that can be used with a variety of commercial products throughout an electronic system design, analysis, verification and implementation flow. Enhancements to UPF in the new standard include support for bias supplies (N-well, P-well, Deep-N-Well, and Deep-P-Well), greater flexibility and capabilities in specification of power states, and enhanced semantic capabilities for merged power domains.

References:
IEEE Standards Association
http://www.accellera.org/activities/p1801_upf/
http://www.accellera.org/join/roster/
http://standards.ieee.org/announcements/pr_ieee1801.html

EDA supporting UPF:

Application engineers (EDN Blog)

2009-07-10T02:53:00.000-07:00

Application engineers

Application engineers are the unsung heroes of EDA. They have to blend the technical skills of designers with the interpersonal skills of salespeople. Most AEs start out as design engineers (or software engineers for the embedded market). But not all design engineers make it as AEs, partially because, as I’m sure you’ve noticed, not all design engineers have good interpersonal skills! There’s also another problem, memorably described to me years ago by Devadas Varma: “they’ve only been in the restaurant before; now they’re in the kitchen they’re not so keen on what it takes to prepare the food.” Being an AE means cutting more corners than being a design engineer, and some people just don’t have that temperament. An AE usually has to produce a 95% solution quickly; a design engineer has to take whatever time it takes to produce a 100% solution.

AEs have a lot of options in their career path. As they become more senior and more experienced they have four main routes that they can take.

Source: EDN

Oasys Design Systems- RealTime Designer - Multi-Million Gate RTL Synthesis

2009-07-10T02:44:00.000-07:00

Introducing RealTime Designer (Connecting RTL to Silicon)
(Oasys Design Systems)

Oasys was founded in 2004 by a team of leading EDA developers, funded by successful entrepreneurs from the IC design and EDA business, with the intent of creating a new platform for IC implementation to address the 65 nanometer and below technology.

RealTime Designer operates at the RTL level and delivers stunning quality of results while doing it at speeds previously thought impossible and with a capacity of 100 million gates

Simply stated, RealTime Designer is a full chip, physical RTL synthesis product that provides a new platform for nanometer design delivering the following capabilities:

20X - 60x run time advantage over existing tools
Best quality of results
Chip scale capacity
Plug and play with existing EDA flows
Day one usability
Dramatic reductions in P&R run times
The best starting point for physical implementation

EDA Blog: (Source: Ken Cheung)

RealTime Designer follows a “Place First” methodology that takes the RTL, partitions it into blocks, places the RTL in the context of a floorplan and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. During the optimization phase, RealTime Designer will repartition the design at the RTL and re-implement until the chip-level constraints are met.

Design teams must manually check for many results, such as design congestion, and send the design repeatedly through synthesis and layout. RealTime Designer is the first product to automate that process. Designers can give RealTime Designer the chip floorplan as input or, if no floorplan exists then Oasys will create a floorplan including macro, pin and I/O placement. At completion RealTime Designer produces a placed design and a netlist that meets the constraints in the context of the desired floorplan.

Synthesizing a physical block using TSMC 65nm – 700k instances, 70 Macros, running at 600MHz, and a “golden” floorplan – RealTime Designer completed the task in just 20 minutes and achieving design closure after a single iteration in place and route. In the traditional approach on the same design, a single iteration of synthesis took 14 hours. Furthermore, it took 6 months of iterations to achieve the best result of -300ps Worst Negative Slack, and in the end was not able to achieve design closure.

Real Time Designer takes in standard inputs, including Verilog, standard timing and physical libraries, SDC timing constraints, and floorplan. VHDL will be available later this year. Output has been tested through all the popular place and route systems.

Competitors:
Synopsys | Cadence | Magma

Related Info:

products

VLSI Conference - Call for papers - January 3-7, 2010

2009-06-26T01:00:00.000-07:00

Submission site now open:
Please make all submissions at https://cmt.research.microsoft.com/VLSI2010/

There are individual tracks for submission

Papers (includes regular papers, proposals for special sessions, panels, embedded tutorials)
Full-day and Hands-on Tutorials
Design-EDA-Systems Contest

IMPORTANT: Last date for all submissions is July 10, 2009

Submission Guidelines

Submission guidelines for tutorials are now available at
http://www.vlsiconference.com/vlsi2010/call_callfortutorials.html

Submission guidelines for papers are available at
http://www.vlsiconference.com/vlsi2010/call_callforpapers.htm

IMPORTANT DATES
Submissions:
Regular Papers	:	July 10, 2009
Special sessions	:	July 10, 2009
Full-day tutorials	:	July 10, 2009
Embedded tutorials	:	July 10, 2009
Panel proposals	:	July 10, 2009
Acceptance notification	:	September 15, 2009
Fellowship application due	:	October 1, 2009

Source: VLSIConference

Runtime Design Automation - FlowTracer

2009-05-08T02:33:00.000-07:00

Runtime Design Automation was founded in May, 1995 in Alameda, CA. Runtime Design Automation's main offices are now located in Santa Clara, CA. The company is privately held and privately funded.
The innovative technology behind our Flowtracer design flow manager comprises run-time tracing for design management. This technology was initially developed at the University of California at Berkeley between 1989 and 1991; it was extended and tested at Siemens from 1992 to 1995.
Runtime Design Automation was issued U.S. Patent 5,634,056 in May, 1997 on intelligent change propagation.
In December 2000 Runtime Design Automation opened a Research and Development office in Padova, Italy. The Italian group was reabsorbed by the California team in 2005.
Products Overview:

LicenseMonitor
License Monitoring. This is our subsystem to monitor licenses (including FLEXlm) and all other design resources, such as machines, file systems, processes.
NetworkComputer
Network Computing. This is our batch processing system, based on the FlowTracer technology It is targeted for the efficient utilization of hardware and software computing resources at the corporate level. NetworkComputer also allows static definitions of flows.
FlowTracer
Workflow Management. This is the solution for total management of complex workflows. A unique technology, called Runtime Tracing™ guarantees the correctness of the flow representation and its efficient execution (see our white paper for info). A patented technique known as Runtime Change Propagation Control allows FlowTracer to move beyond file timestamps and use, for example, MD5 signatures to determine changes to files.

All software is supported on AIX, HPUX, MAC OS-X, Linux, Solaris, Windows (NT,2000,XP).

EDA Utilities by Eng Han

2009-05-01T11:46:00.000-07:00

A lot of EDA tools are used in the design and implementation of IC chip. While the EDA tools are powerful, there are always features that are not available to address some of the IC design and implementation needs. Some of these missing features can be easily developed in a short time while some may take a longer time. The latter forms the niche for EDA Utilities.

CMOS Transistor Layout KungFu

Gate To GDSII

EDA Tools from EDA-Utilities:

Source: http://www.eda-utilities.com/

VLSI Video Lectures from NPTEL (from IIT/IISc)

2009-03-30T10:10:00.000-07:00

VLSI Design - Video Lectures from NPTEL (from IIT/IISc)
National Programme on Technology Enhanced Learning (NPTEL)

For more details on NPTEL - visit http://nptel.iitm.ac.in
http://www.youtube.com/user/nptelhrd - YouTube Videos

55 videos

Electronics - Digital VLSI System Design

Lectures by Prof S.Srinivasan,
Dept of Electrical Engineering,
IIT Madras

Play All Share

40 videos

Electronics - VLSI Design

Lecture Series on VLSI Design by Dr.Nandita Dasgupta, Department of Electrical Engineering, IIT Madras.

Play All Share

Source: http://nptel.iitm.ac.in

Fedora Electronic Lab (FEL)

2009-03-25T12:10:00.000-07:00

Fedora Electronic Lab

Design, Simulate and Program electronics.

Created By	Chitlesh Goorah
Brochures	9-slides flyer with images Fabless solutions for fedora users FEL Introduction at Linuxtag2008 - Berlin, Germany FEL Introduction at FOSS.IN 2008 - Bangalore, India FEL Commitment at FOSDEM 2009 - Brussels, Belgium

Fedora's Electronic Laboratory is dedicated to supporting the innovation and development of opensource Electronic Design Automation (EDA) community.

Fedora Electronic Laboratory provides a complete electronic laboratory setup with reliable open source design tools in order to meet one's requirements to keep one in pace with current technological race. Project management tools such as spreadsheet, gantt diagram, mindmapping tools.... are also included.

This Electronic Laboratory can either be deployed by:

yum or
a Fedora Electronic Lab LiveDVD

Introduction

"Fedora Electronic Lab" targets mainly the Micro-Nano Electronic Engineering field. It introduces:

a collection of Perl modules to extend Verilog and VHDL support.
tools for Application-Specific Integrated Circuit (ASIC) Design Flow process to the Fedora Collection.
extra open source standard cell libraries supporting a feature size of 0.13µm. (more than 300 MB)
extracted spice decks which can be simulated with gnucap/ngspice or any spice simulators.
interoperability between various packages in order to achieve different design flows.
tools for embedded design and to provide support for ARM as a secondary architecture in Fedora.(Fedora-arm)

Featured Applications

The Fedora Electronic Laboratory includes design tools for:

What is Fedora

Fedora is a Linux-based operating system.

Fedora is always free for anyone to use, modify, and distribute.

The Fedora Project is out front for you, leading the advancement of free, open software and content.

Technical Support

Please use the Fedora Electronic Lab mailing lists for technical support related to fedora.

History

25 November 2008	FEL 10 Cambridge released
28 August 2008	FAB approved "Fedora Electronic Lab" LiveDVD spin
30 May 2008	FEL 9 Sulphur released at Linuxtag2008
08 November 2007	FEL 8 Werewolf released
16 August 2007	FESCo approved "Fedora Electronic Lab" as a feature

Glossary

ASIC : Application-Specific Integrated Circuit
EDA : Electronic Design Automation
VLSI : Very Large Scale Integration, about 10⁶ to 10⁷ transistors

Source: http://chitlesh.fedorapeople.org/FEL/

Editor - Emacs Learning Curve

2009-02-12T17:07:00.000-08:00

Editor - Emacs Learning Curve

Source: this blog.

PowerDRC/LVS - Physical Verification from Polyteda

2009-02-12T16:49:00.000-08:00

PowerDRC/LVS from Polyteda Software Corporation

Modern and future 45/32 nm and below technologies are bringing new challenges for EDA tools. Physical verification is one of design flow areas where complexity of new processes in layouts combines with huge amount of data. On other hand, semiconductor industry still uses DRC/LVS tools that are based on core algorithms and principles created in last century. It creates significant bottleneck in design process causing losses of time and money for semiconductor companies.

To address requirement of modern and future designs, POLYTEDA Software Corporation is developing next generation physical verification system based on new revolutionary approaches. New tool is using unique proprietary set of algorithms and principles. Among them are processing subset of rules for several layers in “one shot”, parallel and distributed processing based on unique hierarchical approach, dynamic optimization of DRC/LVS process “on fly” using elements of artificial intelligence, and many others.

Usage of new technology allows reach speed close to theoretical limits. Preliminary calculation shows that new tool will be able to process the biggest currently available designs under one hour time limit. Almost linear speed dependency and scalability in handling huge amount of data allows processing layouts 10-100 times bigger than the biggest designs currently available.

PowerDRC will cover all physical verification needs of semiconductor industry at least for next 10-20 years. It is a tool that is going to last practically forever.

Source: http://www.polyteda.com/

Atoptech - APRISA - Place & Route

2009-02-12T16:33:00.000-08:00

ATopTech was founded in 2004 by a team of leading EDA physical design implementation experts expressly to build new technology, from scratch, to deal with these issues design at 90nm and below. Aprisa, the result of these efforts, shipped to customers in December 2006 and has been used successfully in several 65nm tapeouts throughout 2007. Aprisa is currently in active use in several 40nm design efforts.
Aprisa is a complete netlist-to-GDSII physical design solution, including floorplanning, placement, clock-tree synthesis and optimization, global and detailed routing, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV and MCMM analysis. In addition, Aprisa uses state-of-the-art multi-threading and distributed processing technology across the solution to further speed up the process and avoid the exploding runtime issues with modern nanoscale design.

Interconnect Centric "Precision Optimization"

Precision optimization is a new technology that allows Aprisa to do optimization based on much more accurate information than tools in the past. Rather than using very pessimistic models or using a margin based approach, precision optimization is based on very accurate 2.5D parasitic extraction (which is multi-threaded) and SI analysis that is based on near detail route level accuracy. This optimization happens through out the flow, during placement, CTS, and both global route and detailed routing.

Floorplanning

Aprisa provides an easy-to-use frontend for working out the floorplan of your chip. The initial floorplan may be read in from DEF or created based on user parameters input. Supports:

Channeled and channel-less floorplans, or a mix of both,
Rectilinear floorplans,
Multiple libraries, and multi-height standard cells.
Parametric route for power/ground grid creation

Macro placement is automatic by default, but Aprisa also enables a designer to manually place macro cells through the graphical user interface (GUI).

Placement and Optimization

Aprisa´s placement technology is a timing and congestion driven analytical based placer. The placer calls the timing analysis engine frequently to dynamically obtain and update the best net weightings throughout the flow. The timing engine iterates intelligently between wire-length, routing congestion, and other critical factors to achieve optimal timing for the block/configuration under consideration. Supports:

Complex floorplan / placement constraints including rectilinear regions, multi-height cells, and mixed/overlapping sites,
Efficient High Fan-out Synthesis
Leakage power optimization
Area Recovery

Clock Tree Synthesis (CTS) and Optimization

Aprisa´s sophisticated CTS engine handles scenarios for complex designs. Optimizing for both area and leakage power, it minimizes the number of buffers. The CTS engine does optimization for skew, minimization of global skew and inter-clock skew and supports useful local skew control for overall timing optimization. In addition, the engine supports:

Cluster-based clock trees or meshes
Gated and generated clocks
Synchronization of generated clock pins
Automatic clock gate cloning and de-cloning
Matching of latency targets specified by user for any pins
Automatic creation of special routing constraints (layer, double width/spacing/via, shielding, etc.)
Low-Power Clock Tree Synthesis

Additionally, the Clock Tree Browser GUI provides sophisticated features such as cross-probing and editing on the fly such as resizing clock buffers or moving clock buffer/leaf cell to different levels. It provides detailed delay, transition, skew and load information for each node; and can find or highlight any max or min path to calculate local skew.

Timing Analysis

Aprisa includes a next generation timing analysis engine which correlates extremely well to the industry standard sign off tools.

Features

Very fast, typically 5 minutes per million instances
Read SDC natively without any translation
Tight correlation to Primetime-SI and CeltIC
Native OCV timing analysis
CRPR Support (clock reconvergence pessimism removal)
Timing browser (see diagram)

Multi-corner Multi-mode Analysis (MCMM)

Global Route and Optimization

Detailed Route and Optimization

Features

Multi-threaded engine with near linear performance. An 8 cpu machine will achieve 7-7.5X the performance of a single CPU. Routes 250K instance in about 5 minutes on an 8 CPU machine.
Supports all 90/65/45nm design rules
Supports special routing rules such as double wide, double spaced, shielding, double vias, etc.
Support for DFM issues such as wire-spreading, double-vias, and complex design rules such as end-of-line spacing/extension, min edge, min enclosure, etc.
All routing done in-route rather than post processing steps
Can iterate with precision optimization and MCMM timing engine for optimal results.

The benefits of this approach, that is, a fully "from the ground up" development of a physical-synthesis environment to address the most complex problems in nanoscale chip design, are clear and compelling. Faster design closure, faster project completion, higher performance AND lower power consumption in the final product, and best of all, no surprises, are available to the designer using this state-of-the-art physical synthesis environment.

See Also:
ATopTech Closes Successful 2008, Reaches Revenue Milestone
Atoptech News

Source: Atoptech

FireBolt - Digital IC Thermal Analysis

2009-02-12T16:15:00.000-08:00

- Digital IC Thermal Analysis

The FireBolt thermal simulator computes full-chip temperatures with resolution down to the device and interconnect levels, and integrates smoothly into standard digital IC design flows. The software is fast and scalable, with the capacity to handle very large designs.

The output is a full-chip, 3-D temperature map, which can be used to reveal hotspots and excessive temperature variations. The temperature data also can be used to add thermal awareness to power, timing and electromigration analysis tools.

Adds thermal awareness to power and timing analysis

Adds thermal awareness to electromigration analysis

To run FireBolt, you need to provide a thermal technology file (die stack-up) for the foundry process, and thermal information for the package. FireBolt obtains the design layout and the power source information from your design environment to create a full 3-D temperature analysis of the design. It outputs instance-specific temperatures, wire temperatures and device powers. This information can be annotated into simulation to determine the thermal impact on the circuit's performance and reliability.

FireBolt is intended for use at several points in the design flow, from floorplanning to final sign-off. In the early front-end stage it makes use of information at the block-level, such as the area estimates and power estimates. In the later, back-end stages, FireBolt has the capacity to complete the full analysis, even with many more metal shapes and large number of instances and their power dissipations.

Gradient is unique in its ability to calculate interconnect temperatures due to Joule heating, which allows designers to evaluate the impact on reliability due to electromigration failure.

FireBolt takes into account the influence of the package thermal characteristics on the die temperatures.

FireBolt runs in multiple modes that allow the user to trade off between speed and accuracy, and enables control on the levels of resolution.

More...
http://www.gradient-da.com/tech/firebolt.htm

Also see: CircuitFire

Source: Gradient Design Automation

Toped - IC Layout Editor

2008-12-28T20:52:00.000-08:00

Toped is a cross-platform IC layout editor supporting GDS and CIF formats. It is an open source project licensed under the GNU General Public License. The project is under active development.

Toped is driven by a build-in script interpreter. The script is designed to code and facilitate the layout generation and is used also for configuration. Automatic session recovery, undo with unlimited depth and customizable GUI are among the product features.

Toped focuses on rendering speed and quality of the screen output. The project uses the full power of OpenGL in terms of speed as well as unrestricted number of colours and fill patterns.

News
Toped 0.9.2 is released. The highlights:

CIF import/export
GDSII interfaces now take into account DATATYPE records

Quick links

Downloads - see also FAQ page
- Linux package
- Windows package
Toped development page
Toped wiki page
Toped development mailing list
subscribe to Toped development mailing list

Contributing

Bug reports & ideas - The feedback is more than welcome. Bug reports can be submitted directly to the Berlios site. Alternatively use the development mailing list. Please include session log files with bug reports.
GDSII & technology files - GDSII files from different tools will help to test the project better. Files not covered by non disclosure agreements or similar legal obligations and which can be used for snapshot or demo purposes will be highly appreciated. Naturally credits will be given to the submitters.
Packaging - Toped is already a proud member of Fedora Extras repository. We will be happy to get in touch with the packagers of other Linux distros.
Development - If you feel like joining us - you are very welcome. The project has long enough TODO list yet is still wide open for new ideas.

More information:
Source: http://www.toped.org.uk/
Also see: Fedora Electronic Lab (FEL) - http://chitlesh.fedorapeople.org/FEL/index.html

Free 45nm Open Source Digital Cell Library - Nangate

2008-12-27T20:21:00.000-08:00

Free 45nm Open Source Digital Cell Library - Nangate

The Nangate Open Cell Library is a generic open-source, standard-cell library provided for the purposes of research, testing, and exploring EDA flows. This library is purposely non-manufacturable.

Read the press release from March 3, 2008.

Library Overview

The Nangate Open Cell Library is a generic open-source, standard-cell library provided for the purposes of research, testing, and exploring EDA flows. This library is purposely non-manufacturable.

Nangate has developed and donated this library to Si2 for open use. The library is intended to aid university research programs and organizations such as Si2 in developing flows, developing circuits and exercising new algorithms. In its first release the Open Cell Library contains 38 different functions ranging from buffers to scan flip-flops with set and reset. All the different cell functions come in multiple drive strength variants end up with more than 100 different cells in the library.

The library was generated using Nangate's Library Creator™ and the 45nm FreePDK Base Kit from North Carolina State University (NCSU) and characterization was done using the Predictive Technology Model (PTM) from Arizona State University (ASU). The FreePDK Base Kit is supported by Professors Rhett Davis and Paul Franzon and their research teams and is also available for download.

Because the library was generated using a non-optimized Open PDK, it was not created to be an optimized library for any real-life applications.

Benchmarking of this library against any other library makes no sense and any use for comparisons are hereby prohibited. The use of this library for commercial tool benchmarking is also prohibited.

The library will be enhanced over time based on user suggestions and requests. If you have suggestions for development of the library then please submit them to the project New Feature Request tracker. Report bugs in our Library Bug tracker and join the Library Discussion Forum to solicit help and suggestions from other library users.

Library Contents

The PDKv1.2_v2008_10 release of the Open Cell Library contains the following updates:

Added clock gates with and without test as new functions to the library
Added tabs to all filler cells
Updated OpenAccess views to support Cadence SoC Encounter 6.2 platform
Updated layouts (GDS) to ensure all ports were on grid
Updated LEF views to avoid issues seen with various Place & Route flows

The PDKv1.2_v2008_05 release of the Open Cell Library contains the following views:

Liberty (.lib) formatted libraries with CCS Timing, ECSM Timing and NLDM/NLPM data (fast, slow and typical corners)
Geometric library in Library Exchange Format (LEF)
Simulation libraries in Verilog and Spice (pre and post parasitic extracted netlists)
Cell layouts in GDSII Schematics
Library databook in HTML/XML format
OpenAccess database containing layouts and netlists

The v1.0 20080225 release Open Cell Library contains the following views:

Liberty (.lib) with NLDM/NLPM
LEF View
Verilog
Spice netlists
GDSII
Schematics
Library databook in HTML/XML format

Nangate FreePDK45 Library: PDKv1_2_v2008_10_SP1 (Oct 23, 2008)

Source & References:
https://www.si2.org/openeda.si2.org/projects/nangatelib/
http://www.nangate.com/index.php?option=com_content&task=view&id=137&Itemid=132

Open Library: http://www.nangate.com/openlibrary
Nangate Library: https://www.si2.org/openeda.si2.org/projects/nangatelib/

Book: Processor Design: System-On-Chip Computing for ASICs and FPGAs

2008-12-27T12:22:00.000-08:00

Processor Design: System-On-Chip Computing for ASICs and FPGAs

Author: Jari Nurmi

Paperback: 528 pages

Publisher: Springer

ISBN: 1402055293

File Format: PDF

File Size: 14.2 MB

Description: Processor Design addresses the design of different types of embedded, firmware-programmable computation engines. Because the design and customization of embedded processors has become a mainstream task in the development of complex SoCs (Systems-on-Chip), ASIC and SoC designers must master the integration and development of processor hardware as an integral part of their job. Even contemporary FPGA devices can now accommodate several programmable processors. There are many different kinds of embedded processor cores available, suiting different kinds of tasks and applications.

1. Download Link

2. Download Link

What Every RF Engineer Should Know: RFID

2008-12-27T12:12:00.000-08:00

What Every RF Engineer Should Know: RFID

December 27th, 2008

RFID is hot on the RF DesignLine, so I had a virtual "sit down" with some leaders in the industry to see where the technology is, and where they think it is going. The following article includes some of the thoughts and remarks of Todd Humes, Senior Director, Engineering Embedded NVM Group, Virage Logic Corporation; Darren McCarthy, Technical Marketing Manager, RF Test, Tektronix, Inc; Jeff Miller, Product Manager Tanner EDA; David Hall, Product Manager, National Instruments RF & Communications; and Dirk Morgenroth, Marketing Director, RFID, NXP Semiconductors.

After the interview, I’ve included some links to some of the most popular RFID articles on the site.

RFDL: What is the status of the technology?
Humes: RFID technology continues to become more prevalent as standards-based designs reduce die cost and drive broader market adoption. ISO standards 14443, 15693, and 18000 have created opportunities for companies to enter the RFID space without forcing proprietary solutions onto their customers.

McCarthy: RFID technologies are becoming ubiquitous. The cost and benefits of various RFID technologies have enabled the adoption in homes, cars, documents, animals, and phones. Tire pressure monitoring systems (TPMS) have been mandated on all cars for safety concerns about the operating pressure of our tires. Passports issued worldwide in recent years have all migrated to the ISO 14443 "proximity" RFID standard to simplify and coordinate worldwide immigrations. There is no single RFID technology that can fulfill all applications. Near Field Communications (NFC) on mobile phones and UHF RFID technologies for tracking cargo shipping containers need to operate over different distances and temperature ranges, and the amount of data and security are defined by the end-use application of an RFID technology.

Miller:RFID tags are used in a wide variety of applications around the world, and their use is expected to explode as the unit costs decrease and new markets open up.

Hall: RFID adoption is still sometimes limited by tag manufacturing costs and the need for better understanding of UHF signal propagation. However, it seems that greater awareness of the technology’s benefits is needed in order to drive widespread adoption. I am continually amazed at the new applications people are able to solve with RFID. And, further improvements in RF performance will naturally occur as a result of increased awareness.

More... - Click Here

Other Related Articles from "RFEngineer"

Source: http://www.rfengineer.net/

Intro to low-power design

2008-12-23T20:26:00.000-08:00

Intro to low-power design

This article explains the basics of low-power design. Topics covered include sleep modes, memory system design, systems clocks and real-time clocks, and power over USB.
By David Katz and Rick Gentile, Analog Devices, Inc.

No embedded design is complete without a thorough analysis of power. This goes without saying for battery-operated devices, but it also holds true for wired systems. Power has thermal, volumetric, and financial impacts in all systems—wired or wireless.

In this article, we will consider different areas that impact power dissipation and show you how to save power. We will focus on the processor and its surrounding hardware ecosystem because these components usually consume a significant share of power. In addition to helping you save power, this knowledge will also aid in processor selection.

What is "low power?"
Before we go any further, a discussion of terminology is in order. "Energy" relates to the total amount of work performed, whereas "power" measures the rate at which the work is performed (energy per unit time). In electronics, energy = power × time and power = voltage × current.

System designers usually are concerned with both total energy dissipation and peak power dissipation. In other words, energy use is what drains a battery, but the battery needs to provide enough instantaneous power to meet peak demands. Our convention will be to focus on power dissipation, since this is prevalent terminology in the industry. However, we're really referring to both energy and power when we use the term "power."

So what does "low power" mean? In embedded systems, the term is relative. At the extreme low end of the power scale, we have applications that run from a watch battery. At the other extreme, we have line-powered systems that need to minimize power to avoid the cost of heat sinks, fans, regulators, and so on.

Many of today's designs—from automotive radios to instrumentation boards in a "card cage"—are built from specs handed to OEMs. These specs often describe a strict power budget allocation in order to ensure compliance across vendors. The point is that a system does not have to be battery-powered or mobile to care about lowering power consumption.

There are a number of ways to tune the power profile of a system to meet an application's requirements. They include:

Dynamically changing frequency and voltage
Understanding a processor's separate power domains
Profiling code to optimize for power in a targeted fashion
Using a processor's power modes
Considering system-level contributions to power consumption

Below, we'll focus on the last two bullets. The source listed in the References section provides more detail on the other topics.

Click here for more on,

Power Modes - Full, Sleep/Stand-By, Hibernate
Taking Advantage of Power Modes
Optimize power for Applications

Source: DSPDesignLine - http://www.dspdesignline.com/

Related Links:
Low Power Articles/Blogs: http://www.edn.com/hot-topic/48879/Low-power%20design.html

Code and Functional Coverage - Why Both?

2008-12-17T02:36:00.000-08:00

The Quality of Verification is measured through "Coverage". Lets understand why coverage than what is coverage? Generally, when we verify the DUT, we build test cases and run all possible test scenarios on the DUT, but how to prove that we have verified the DUT thoroughly? So here comes the term "Coverage". Coverage is the measurement of how much of the Design functionality exercised by the verification environment. In simple terms, its a way proving others that you have verified all the functionality and exercised all the codes of the DUT using the verification environment.

EDA Tools:

ICCR ( Cadence)
ModelSim (Mentor Graphics)

Coverage can be divided into two:

Code Coverage
Functional Coverage

RTL verification is said "completed" when we get (98-100)% Code coverage and 100% Functional Coverage.

Code coverage is further divided into

Block Coverage
Expression Coverage
FSM Coverage
Toggle Coverage

The term Functional Coverage is the measurement of functionality exercised by the verification environment and the term Code Coverage is the measurement of how much of the Design code exercised using the verification environment. It is very important to have good Code and Functional Coverage. Note it I have written good Code and Functional Coverage. So your next question is why Both? Lets have detailed understanding of why both Functional and Code coverage which was the main intent of this topic. Functional coverage alone is not enough to prove verification completion as with few test cases you can easily exercise the functionality of the design but whether you have exercised all the lines/branch/condition/FSM/Toggles of the Design using verification environments is determined through Code Coverage. Functionality of the design can be checked , but code coverage measures how good is your test environment.

Example for Code coverage: DUT (4:1 Mux )

module four_mux ( a, b, c, d, Sel_a, Sel_b , Out );
input a, b, c, d, Sel_a, Sel_b ;
output Out ;
reg Out ;
always @ ( a, b, c, d, Sel_a, Sel_b)
begin
case (Sel_a, Sel_b)
2'b00 : Out <= a; 2'b01 : Out <=b; 2'b10 : Out <=c; 2'b11 : Out <= d; default : Out <= 1'b0; endcase end endmodule

Test Case to verify 4:1 Mux

module tb_four_mux ;
reg a, b, c, d, Sel_a, Sel_b ;
wire Out ;
initial begin
a = 1'b0 ;
b = 1'b1 ;
c = 1'b0 ;
d = 1'b1 ;
// Input Combination 0
Sel_a = 1'b0 ;
Sel_b = 1'b0;
//Input Combination 1
Sel_a = 1'b0 ;
Sel_b = 1'b1 ;
//Input Combination 2
Sel_a = 1'b1 ;
Sel_b = 1'b0 ;
//Input Combination 3
Sel_a = 1'b1;
Sel_b = 1'b1;
//Input Combination X
Sel_a = 1'bx ;
Sel_b = 1'bx ;
end

//Instantiate the DUT in test bench environment
four_mux four_mux_instantiate ( .a (a),
.b (b),
.c (c),
.d (d),
.Sel_a (Sel_a),
.Sel_b (Sel_b),
.Out (Out)
);
endmodule

Let us assume that input combination x is not written in test case. So now the input combination 0, 1, 2, 3 hits the functionality of the DUT,

always @ ( a, b, c, d, Sel_a, Sel_b)
begin case ( Sel_a, Sel_b )
2'b00 : out <= a ;
2'b01: out <= b ;
2'b10: out <= c;
2'b11: out <= d;
default : out <= 1'b0 ;
endcase
end

So, depending upon the Sel_a and Sel_b, the particular input would be driving the output which is the functionality of the Mux. So, if Sel_a and Sel_b equals to 0, input a Out, when Sel_a and Sel_b equals to 1, input b would be driving the Out, when Sel_a and Sel_b equals to 2, input c would be driving the Out and when Sel_a and Sel_b equals to 3, input d would be driving Out. This is the functionality of the Design MUX. With the test input combination 0, 1 , 2 and 3 we check the functionality of the mux and we get 100% Functional Coverage but we have not exercised the statement default so our code coverage would be 85.75% (6/7 * 100). So with the code coverage percentage, we understand that we have not exercised certain Condition or codes of the Design. We improve our test environment to check whether our test case hits the default statement. Through this we get 100% code coverage and a proof that we have verified the RTL thoroughly.

Coverage obtained through Assertion is always Functional Coverage as we check the property of the Design. Code Coverage is checking how good is your testcase and how much RTL is exercised.

So, we conclude that Verification is DONE when we hit 100% Functional and Code Coverage.

About Author:
Jeyanthi Arumugam
Senior Design Engineer in Freescale, Noida

URL: http://vlsi-core.blogspot.com/2008/12/code-and-functional-coverage-why-both.html

ASIC Verification - Why?

2008-12-12T06:14:00.000-08:00

Why ASIC Verification??

People have different approaches for ASIC Verification, but in simple terms "Verification is checking whether the design specification is brought into reality or not". Though today we are in a very fast, competitive, change emerging world where in hourly basis many companies are coming up with new tools and languages, but it solely depends upon users choice which method and language to adapt for his/her design verification environment to turn his/her black and white assumption to a meaningful chip and to promote people using the Chip-Set in various gadget. Though there are many gadgets in the market, companies need to consider the powerful pack of sleeky, user-friendly, all in one, stylish, resolution, clarity, speed and something unique features to attract the people and to survive in this competitive world of Conquer to Destroy.

Of course, the first paragraph was mile deviating from the topic of verification but the end result of verification is the chip and its fantacy in the market. Let's touch our fingers in 'Verification', Verification is not only just 'testcases' and 'testbench' environment. Its even more than the word "Testcases". Even writing testcases is an art, which people need to plan before coding. Then intention of the testcase, whether its precise and hits the corner cases, coverage these are some of the major tips which should be taken care before writing a pattern. "Planning" plays a major role in any kind of environment and then execution of the same is very important as we all know the great saying "Let our advance worrying become advance thinking and planning"

ASIC Verification can be divided into 2 major category

1. Functional Verification

Directed Testcases: (In Verilog and C)
Randomization: Like Vera, System verilog
Assertion: (Like, System Verilog Assertion (SVA), Open Vera Assertion (OVA - Synopsys), Constraint based Verilog (Freescale)

2. Formal Verification

Equivalence Check (EC):Its checking whether the golden design and revised design are same (Cadence Encounter - LEC, Conformal)
Formal Check: Using Synopsys ( Semi-formal tool: Magellan), Cadence (Formal tool: IFV)

Now the word "Functional" and "Formal" may hit your mind what is that?

Functional Verification:

It requires user-defined stimulus which may not be checking all the corner cases and there is a heavy risk of missing some bugs. It depends upon how the user has coded.

Formal Verification:

Its tool based verification where the Design and the assertions are given as input to the tool, and the tool try to do a negative check on the design properties, If the tool fails to prove the property, it will declare Proven else Falsified but still there is a risk of state explosion or deadlock. Note here we do not write any testcases, the tool generates all possible scenerio.

Why we need assertion?

Assertions are really fantastic for detecting and isolating bugs. This increases productivity. The fact that they're re-usable in formal tools and simulators also increases productivity, and helps coverage closure. Assertions can help you monitor interactions between blocks. Suppose block A is driving block B. Assertions can be used to verify the block A interface, and can also be used to verify the assumptions for block B. Assertions can validate and ensure consistency between interfaces when two blocks talk to each other. Assertions: by their nature to find errors. If you miss, they fire – they indicate errors, they indicate the location, and they make debug much simpler.

RTL Verification can be said "DONE" only when we get good code coverage and functional coverage which is 100% (functional coverage) and 97-99 % (code coverage).

Again Coverage is a wide topic, but in general "coverage is percentage of testcases/functionality exercised". Its a wide topic to be discussed offline or on a separate topic.

Once we are done with the RTL verification, synthesis is carried forward to generate Synthesized RTL, Logical Equivalence Check (LEC) is carried to check the logical equivalence between the RTL and Synthesized RTL and checked for any ABORTS. If there are aborts in the design, gate level verification must be carried forward for the early detection of bugs.

So every stage from Specification to Tape-Out (TO), every phase has intensive verification. So by the above mentioned sentence one can roll his sleeve and say Its a very vast field where innovation and creativity is important to hit the bug.

About Author:
Jeyanthi Arumugam
Senior Design Engineer in Freescale, Noida

VLSICore Blog: http://vlsi-core.blogspot.com/

22nd International Conference on VLSI Design & 8th International Conference on Embedded Systems

2008-12-08T00:27:00.000-08:00

22nd International Conference on VLSI Design & 8th International Conference on Embedded Systems

Theme: Improving Productivity Through Higher Abstraction

This joint-conference is a forum for researchers and designers to present and discuss various aspects of VLSI design, electronic design automation, enabling technologies, and embedded systems. It covers the entire spectrum of activities in the two vital areas of VLSI and embedded systems, which underpin the semiconductor industry. The five-day program will consist of regular paper sessions, special sessions, embedded tutorials, panel discussions, design contest, industrial exhibits and two days of tutorials.

The new paradigms in design, EDA and system implementation will be presented and discussed in the 2009 edition of this conference.

Date:
Conference: January 5th - 7th, 2009
Tutorial Program: January 8th - 9th, 2009

Timing:
Venue: Taj Palace Hotel, New Delhi, India
Website: http://vlsiconference.com/vlsi2009/

Entry Fee:

Registration fee for Members & Non-Members:
http://vlsiconference.com/vlsi2009/reg.html

Student Track Registration:
http://vlsiconference.com/vlsi2009/student_track.html

Fellows Registration:
http://vlsiconference.com/vlsi2009/fellows_registration.html

Schedule

Conference Schedule:
http://vlsiconference.com/vlsi2009/confe_conference_schedule.html

Tutorial Schedule:
http://vlsiconference.com/vlsi2009/tutorials.html

International Conference on VLSI and Communication (2009)

2008-12-08T00:23:00.000-08:00

International Conference on VLSI and Communication
Date: 16 to 18 April 2009
Location: Kottayam, Kerala, India

Website: http://icvcom.org
Contact name: Er. Shajimon K John

ICVCOM brings together the international community of researchers and practitioners to discuss the latest advancements and future directions in the areas of knowledge based engineering.

Organized by: SAINTGITS College of Engineering
Deadline for abstracts/proposals: 10 January 2009

Check the event website for latest details.

Design, Automation and Test in Europe (DATE 2009)

2008-12-08T00:14:00.000-08:00

Industry and academia who want to connect with the latest developments in the electronics industry are advised to attend DATE (Design, Automation and Test in Europe) 2009 and consider sponsorship. With just four months to go until DATE09, a leading global electronics event, which will be held in Nice, France from 20-24 April, the conference has received a record number of contributor submissions and a 30 percent increase in papers on industrial applications.

It also offers increased opportunities for sponsorship (available for all budgets) of the DATE industrial exhibition which runs in parallel with the conference.

'DATE 2009 is stronger than ever before and is a truly global event and there is still scope for industry players to sponsor sessions and marketing activities at the conference,' said Professor Bashir M. Al-Hashimi, DATE Technical Programme Chair and Professor of Computer Engineering at the University of Southampton's School of Electronics and Computer Science.

The comprehensive technical programme includes three keynotes delivered by industry and academia leaders:

* Paul Garnier, Chief Technology Officer, Texas Instruments
* Mike Muller, Chief Technology Officer, ARM
* Joseph Sifakis, Verimag Laboratory, Grenoble

"The outstanding 2009 keynote speakers reflect DATE's measured focus on complete system level design, addressing hardware and software challenges, and its increasing stronger ties with key application domains. Our goal is to look beyond the current economic situation, and to create a vibrant meeting place where startups, innovative Electronic Design Automation (EDA) companies, large system houses and researchers can exchange ideas and promote innovation and growth," said Professor Luca Benini, DATE General Chair and Professor of Computer Engineering at Bologna University.

The programme which consists of tutorials and workshops given by researchers and industrialists covers two key themes. The first is a multi-core theme which covers advances and applications including design methods, architectures and programming. The second theme covers systems-on-chip and development of strategies for application-oriented design flows and methods.

The technical programme, features 77 technical sessions covering the latest advances and developments in system design methods and embedded software development validation and test and state-of-the-art industrial applications. Important topics such as the future of FPGA, progress reports on the move to 32 nanometer CMOS, and programming of multiprocessor System-on-Chip platforms will also be debated by leading researchers and developers and industry executives.

DATE 09 will take place at the Acropolis, Nice, France from 20-24 April 2009.

Magma - Blast Fusion

2008-01-01T10:53:00.000-08:00

Blast Fusion® is an advanced netlist-to-GDSII chip implementation system for high-performance, high-complexity and low power designs being implemented in 90-nm and finer process geometries. Blast Fusion delivers complete design closure with better timing, smaller area, lower power, better yield, faster turnaround time and higher capacity than conventional point-tool flows.

Super-high capacity allows designs of up to 5 million gates to be implemented flat on a 32-bit Linux machine, or up to 6 million gates to be implemented flat on a 64-bit Linux machine.Faster runtime is achieved through unified engines and efficient algorithms. 2-milliongate designs can be completed overnight.
Unmatched timing and area results are enabled through the FixedTiming® methodology, SuperCell™ abstraction, integrated clock tree technology, OCV analysis and optimization, and concurrent multi-mode and multi-corner analysis and optimization.
Significant leakage and dynamic power reduction is achieved through an integrated implementation flow using multiple threshold voltage (multi-Vt) cells and multiple voltage support, without sacrificing performance.
Proven 90-nm design support for major silicon vendors and foundries is provided through design rules and design-formanufacturability capabilities.

EDA Vendor: Magma Design Automation - http://www.magma-da.com/
Product Page: http://www.magma-da.com/products-solutions/digitaldesign/blastfusion.aspx
Support: https://molten.magma-da.com/
Tutorials: N/A
Useful Links: N/A
Also see: N/A
Related News:

Search more - here.

Source: Magma Design Automation

Olympus-SoC (Place & Route System)

2008-01-01T04:04:00.000-08:00

Olympus-SoC™ is a complete IC implementation (netlist-to-GDSII) solution targeted at 65nm/45nm designs, which augments Mentor Pinnacle™, the industry’s leading Design for Variability solution.

Olympus-SoC gives designers the ability to optimize designs subject to variations in design modes, as well as lithography and other manufacturing processes windows, in a comprehensive and holistic fashion. Advanced multi-corner, multi-mode, (MCMM) technology provides timing optimization across a large number of design and process corners throughout the design flow, ensuring fast design-for-manufacturing closure. Integral to Olympus-SOC is Mentor's next-generation detailed routing architecture that incorporates variation-aware timing optimization and litho-modeling to address OPC/RET effects early in the design cycle.

With its high capacity implementation architecture, Olympus-SoC provides these advanced capabilities even for the largest designs at 45nm and beyond.

EDA Vendor: Mentor Graphics - http://www.mentor.com/ (Sierra Design Automation)
Product Page: http://www.mentor.com/products/ic_nanometer_design/cl_floorplan/olympus/index.cfm
Support: http://supportnet.mentor.com/
Tutorials: N/A
Useful Links: N/A
Also see: Mentor Pinnacle™
Related News:
Sierra Design Automation Delivers Olympus-SoC Lithography-Driven IC-Implementation System for 65-nm and 45-nm Designs
http://www.soccentral.com/results.asp?CatID=552&EntryID=19653
Mentor's Olympus-SoC Place-and-Route System Slashes Design Closure Times with Parallel Timing Analysis and Optimization Technology
http://www.soccentral.com/results.asp?EntryID=27075

Search more - here.

Source: Mentor Graphics

PrimeTime (PT) - Static Timing Analysis

2008-01-01T03:56:00.000-08:00

Overview
Timing closure in today's advanced designs remains the number one challenge for designers today, especially at 65-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure.

The PrimeTime STA Solution
The Synopsys PrimeTime® static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry's de-facto gold standard for gate-level static time analysis with the capacity and performance for 50+ million-instance chips being designed at 65-nm and below. The PrimeTime solution is a key component of the Galaxy Design Platform.

With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It delivers to designers extensive timing analysis checks, advanced analysis techniques, golden delay calculator, advanced modeling, unmatched productivity and ease of use, a graphical user interface, and industry-wide ASIC vendor sign-off and foundry support.

EDA Vendor: Synopsys - http://www.synopsys.com/
Product Page: http://www.synopsys.com/products/analysis/primetime_ds.html
Tutorials:
http://www.ece.virginia.edu/~mrs8n/cadence/SynthesisTutorials/PrimeTutorial2.pdf
http://www2.informatik.uni-jena.de/~doersing/lehre/ps/sn99.10_dok/static/print/pttut.pdf
Useful Links: N/A
Datasheet: http://www.synopsys.com/products/analysis/primetime_ds.pdf
Recent News:
Search more - link here

Source: Synopsys

RF Tools - Design & Analysis

2007-12-27T12:15:00.000-08:00

RF Design TOOLS

Ansoft Corp.: 412-261-3200, Ansoft / Pittsburgh, PA | Electromagnetic
AppCAD: Hewlett Packard | General design tools
ASM 500: 408-426-6163 | Artwork, Conversion, DFX, Gerber
ATC Quick-Calc: 516-547-5700, ATC / Huntington Station, NY | Capacitor Calculation
AutoCAD: 408-517-1700, AutoDesk, Inc. / Cupertino, CA | Mechanical, Drafting
Avista Design Systems: 800-985-6080, ADS / Folsom, CA | RF, Microwave
AVX SPIMIC: 800-946-0414, AVX / Myrtle Beach, SC | Capacitor Calculation
Calculators: Hundreds of calculators
CapCAD: 315-655-8710, Dielectric Laboratories / Cazenovia, NY | Capacitor Calculation
Cascade Calculator: 770-945-1115, Anadigics / Suwanee, GA | Receiver Cascade Analysis
Control System Professional: 888-899-3407, Wolfram Research | System Analysis
Eagle: 800-858-8355, CadSoft Computer, Inc. / Delray Beach, FL | Layout
Eclipse 4.0: 804-525-6837, Arden Technologies/ Forest, VA | RF Microwave Linear
Electronics Workbench: 800-263-5552, Interactive Image Technologies / North Tonawanda, NY | Analog, Digital, Mixed Mode
ezGuide: 708-349-3300, Andrew Corp. / Orland Park, IL | Microwave Transmission Line Ordering Guide
Ensemble: 303-541-9525, Boulder Microwave Technologies / Boulder, CO | Antenna Design
Fidelity: 510-797-8109, Zeland Software / Fremont, CA | Time-Domain 3D EM Simulation
FilterCAD: 408-432-1900, Linear Technologies / Milpitas, CA | Active filter designer
Full Wave: 514-849-8752, Infolytica |Electromagnetic
Genesys: 770-939-0156, Eagleware Corp. / Stone Mountain, GA | Electromagnetic, Schematic, Layout
HFSS: 412-261-3200, Pittsburgh, PA | Electromagnetic Field Simulation
Hyperlynx: 425-869-2320 | PCB layout signal analyzer
ICAP/4: 800-357-1636 | Circuit simulation
IE3D: 510-797-8109, Fremont, CA |Planar & 3D EM Simulation
IsSpice4: 310-833-0710, Intusoft, San Pedro, CA | Schematic, Circuit Simulation
Macsyma: 800-622-7962, Macsyma, Arlington, MA | Math
Maple: 800-267-6583, Waterloo Maple / Ontario, Canada |Mathematics
MathCad: 617-577-1017, MathSoft / Cambridge, MA | Mathematics
Mathematica: 800-943-9614, Wolfram Research / Champaign, IL | Mathematics
MatLab: 508-647-7000, The Math Works / MA | Mathematics
Maxwell Strata: 412-261-3200, Ansoft Corp. / Pittsburgh, PA | Electromagnetic
Mentor Graphics: 800-547-3000, Wilsonville, OR | Analog, Digital, Mixed Signal
Microstrip Calculator: Max Froding | Microstrip line calculator
Microwave Explorer: 201-881-1200, Compact Software / Paterson, NJ | Electromagnetic, RF, Microwave
Microwave Office: 310-726-3000, El Segundo, CA | Electromagnetic, RF, Microwave
Microwave System Planner: 708-349-3300, Andrew Corp. / Orland Park, IL | Microwave System Planning
MxrSpur: 408-445-2902, The Engineers Club | graphical mixer spurious analysis
MMICAD: 800-671-9505, OR | Electromagnetic, RF, Microwave
PADS-Power Suite: 800-554-7253 | Schematic Capture, Layout, Routing
p-cad 2000: 800-488-0680, San Diego, CA | PCB layout
Parts&Vendors: 800-280-5176, Grass Valley, CA | Parts Lists
Protel : 800-544-4186, Provo, UT | Schematic Capture, Simulation, Layout
PSI Select: 708-349-3300, Andrew Corp. / Orland Park, IL | Pressurization Guide
Radio Designer: 860-594-0200, ARRL/Newington, CT | RF CAD
Serenade 8.5 PC for Windows NT: 412-261-3200, Ansoft / Paterson, NJ | Schematic Capture, Simulation, Layout
SpectreRF: 800-746-6223, San Jose, CA | RF Integrated Circuit
SISP: +30-1-772 1482, MCDG / Athens, Greece |Spiral Inductor Simulation
Sonnet Level 1: 315-453-3096, Sonnet Software / Liverpool, NY | Electromagnetic
SysCad: 414-367-6825, Brookfield, WI | System, Filter
SysCalc: 804-525-6837, Arden Technologies / VA | RF, System Simulator
System View: 818-597-1414, Elanix / Westlake, Village, CA | DSP, Communication, Signal Processing, Control
TESLA: 800-631-1113, Tesoft, Inc. / Roswell, GA | System Simulator
VIEWLogic: 800-873-8439, ViewLogic / Marlborough, MA | ASIC, FPGA, PCB Layout
VSWR Calculator: 707 538-5825, VNA Help, Santa Rosa, CA | VSWR conversion calculator

Source: http://www.rfengineer.net/rf-tools/

List of Achronyms in VLSI

2007-01-10T02:47:00.000-08:00

Glossary in VLSI
http://parts.jpl.nasa.gov/asic/Glossary.html

List of VLSI Acronyms:

A/D: Analog to Digital
ASIC: Application Specific Integrated Circuit
ATPG: automatic test pattern generation
BILBO: built-in logic block observation
BIST: built-in self-test
CAD: computer-aided design
CAE: computer-aided engineering
CAT: computer-aided testing
CDR: critical design review
CE: concurrent engineering
CLB: Configurable Logic Block
CMOS: Complimentary Metal Oxide Semi-conductor
CPLD: Complex Programmable Logic Device
CPU: central processing unit
CSA: Carry Save Adder
CSD: Canonical Signed Digits
CZT: Chirp-z Transform
DCM: Digital clock Manager
DESC: Defense Electronics Supply Center
DFT: design for test
DFT: Discrete Fourier Transform
DRC: design rule check
DSP: Digital Signal Processing
ECL: emitter-coupled logic
EDA: electronic design automation industry
EDAC: error detection and correction
EDIF: electronic design interchange format
EEPROM: Electrically Erasable Programmable Read Only Memory
EPROM: Electrically Programmable Read Only Memory
ERC: electronic design augomation
FDL: fault detection and localization
FFT: Fast Fourier Transform
FIR: Finite Impulse Response
FPGA: Field Programmable Gate Arrays
FPLD: Field programmable Logic Devices.
GA: gate array
GaAs: gallium-arsenide
HDL: hardware description language
HOL: high-order logic
I/O input/output
IEEE Institute of Electrical and Electronics Engineers
IIR: Infinite Impulse Response
ISE: Integrated Synthesis Environment
JAN Joint-Army-Navy
JEDEC Joint Electron Device Engineering Council
JTAG Joint Test Action Group
LAB: Logic Array Blocks
LC: Logic Cell
LCC leadless chip carrier
LE: Logic Element
LET linear energy transfer
LFSR linear feedback shift register
LSB: Least Significant Bit
LSSD level-sensitive scan design
LTI: Linear Time Invariant
LTPD lot tolerance percent defective
LUT: Look-Up Table
MAC: Multiply Accumulate
MAG: Multiplier Adder Graph
MAX: Multiple Array Matrix
MSB: Most Significant Bit
NRE nonrecurring engineering (charges)
PAL: Programmable Array Logic
PDA percent defective allowable
PDR preliminary design review
PG pattern-generation (tape)
PGA pin grid array
PIA: Programmable Interconnect Array
PLA: Programmable Logic Array
PLL: Phase Locked Loop
PM parametric monitor
QCI quality conformance inspection
QCRIT critical charge
QML Qualified Manufacturers List
QMP Quality Management Plan
QPL Qualified Products List
RAG: Reduced Order Graph
RAM: Random Access Memory
ROM: Read Only Memory
RTL register-transfer level
SC standard cell
SD: Signed Digit
SEC standard evaluation circuit
SEE single-event effect
SEL single-event latchup
SEU single-event upset
SMD standardized military drawing
SOC: System On Chip
SOI silicon-on-insulator
SOS silicon-on-sapphire
SOW statement of work
SPC statistical process control
SPICE simulation program with IC emphasis
SRAM: Synchronous Random Access Memory
SRL shift register latch
TAP test access port
TCI technology conformance inspection
TCV technology characterization vehicle
TDDB time-dependent dielectric breakdown
TID total ionizing dose
TMT triple modular redundancy
TQM total quality management
TRB technology review board
TRSL test requirements and specification language
TTL transistor-transistor logic
VHDL: VHSIC Hardware Descriptive Language
VHSIC: Very High Speed Integrated Circuit
VLSI: Very Large Scale Integrated Circuit
WAVES waveform and vector exchange program

Courtesy/Source: NASA

IBM: ASIC Design & Testing

2006-08-04T03:40:00.000-07:00

IBM ASIC Design & Testing

Here is TOC of the IBM Design & Testing Methodology for ASIC Design.
Source: http://www.research.ibm.com/journal/rd40-4.html

IBM ASIC design and testing
Vol. 40, No. 4, 1996
Order No. G322-0204

The papers in this issue describe some of the methodologies and tools recently developed by IBM for use in ASIC (application-specific integrated circuit) design, as well as some applications to actual product design for both IBM and IBM customers.



	HTML PDF


	Papers may be viewed by clicking on the title of interest

Preface	E. P. Hsieh and M. D. O'Neill	p. 376


Technology-migratable ASIC library design	T. R. Bednar, R. A. Piro, D. W. Stout, L. Wissel, and P. S. Zuchowski	p. 377


Design methodology for IBM ASIC products	J. J. Engel, T. S. Guzowski, A. Hunt, D. E. Lackey, L. D. Pickup, R. A. Proctor, K. Reynolds, A. M. Rincon, and D. R. Stauffer	p. 387


BooleDozer: Logic synthesis for ASICs	L. Stok, D. S. Kung, D. Brand, A. D. Drumm, A. J. Sullivan, L. N. Reddy, N. Hieter, D. J. Geiger, H. H. Chao, and P. J. Osler	p. 407


Design planning for high-performance ASICs	J. Y. Sayah, R. Gupta, D. D. Sherlekar, P. S. Honsinger, J. M. Apte, S. W. Bollinger, H. H. Chen, S. DasGupta, E. P. Hsieh, A. D. Huber, E. J. Hughes, Z. M. Kurzum, V. B. Rao, T. Tabtieng, V. Valijan, and D. Y. Yang	p. 431


Circuit placement, chip optimization, and wire routing for IBM IC technology	D. J. Hathaway, R. R. Habra, E. C. Schanzenbach, and S. J. Rothman	p. 453


Test methodologies and design automation for IBM ASICs	P. S. Gillis, T. S. Guzowski, B. L. Keller, and R. H. Kerr	p. 461


IC technology and ASIC design for the Cray J90 supercomputer	D. J. Poli, M. S. Berry, and J. N. Kruchowski	p. 475


Design considerations for Digital's PowerStorm graphics processor	C. Gianos and D. Hobson	p. 485


PowerPC AS A10 64-bit RISC microprocessor	J. W. Bishop, M. J. Campion, T. L. Jeremiah, S. J. Mercier, E. J. Mohring, K. P. Pfarr, B. G. Rudolph, G. S. Still, and T. S. White	p. 495


Recent IBM patents		p. 507

SoC EDA Tools

2006-07-15T02:02:00.000-07:00

EDA Tools used at Various stages of SoC Design Flow
Source: http://groups.yahoo.com/group/VLSICore

SoC Flow

Architecture & Specification
Layout & Library Development

CosmosLE/SE [Synopsys]

Virtuoso [Cadence]

ICstation [Mentor Graphics]

L-Edit [Tanner]

MicroWind [MicroWind]

LASI [University of Berkeley]

Magic []

Electric []

Alliance [open source, Pierre et Marie Curie University, Paris]

Library Characterization

Star-MTB [Synopsys]

NanoChar [Synopsys]

Library Characterizer [Nangate]

FRONTEND Flow
RTL Coding

vi/emacs Editor [unix]

Cadence Composer [Cadence]

HDL - Verilog/VHDL/System Verilog

Actel Libero

Altera Quartus II

Altium Nexar

ArchPro MVSIM

Arithmatica CellMath Designer

Axiom @Verifier

Calypto SLEC

Certess Certitude

CLKDA Amber

Concept Engineering RTLVision PRO

DAFCA ClearBlue

DeFacTo Scan Insertion

EVE ZeBu

GateRocket RocketDrive

HDL Works HDL Companion

Jasper JasperGold

Lattice ispLEVER

Liga Systems NitroSIM

Magma Quartz Formal

NEC CyberWorkBench

Philips ED&T RTL DfT

ProDesign CHIPit

Prover eCheck, sCheck

Real Intent Verix

S2C TAI IP

Sequence Power Theater

Silicon Navigator Rocket

Tenison VTOC

Tharas Systems Hammer

Theseus Logic NCL-shell

Scan Insertion

DFT Compiler [Synopsys]

DFT Advisor [Mentor Graphics]

Formal Verification

VCS [Synopsys]

Formality [Synopsys]

Conformal LEC [Cadence]

Verplex [Verplex]

FormalPro [Mentor Graphics]

Simulation

VCS - Vera [Synopsys]

NC-Verilog / Verilog XL [Cadence]

finsim [Fintronics]

Event Simulation - MTI VHDL Model Sim [Mentor]

Event Simulation - VSS {VHDL} [Synopsys]

Event Simulation - Verilog - Verilog XL [Cadence]

Event Simulation - Verilog - MTI Model Sim Plus [Mentor]

Event Simulation - Verilog - VCS [Synopsys]

Veriloger []

Synthesis

RTL Compiler [Cadence]

Design Compiler [Synopsys]

DC Expert for ASIC [Synopsys]

Blast RTL [Magma]

Exempler for FPGA

Leornado Spectrum [Mentor]

Alliance [open source, Pierre et Marie Curie University, Paris]

FPGA Synthesis

Quartus []

Xilinx [Xilinx]

DC-FPGA [Synopsys]

Precision Synthesis [Mentor Graphics]

ATPG and Tests

Tetra Max [Synopsys]

DFT Compiler [Synopsys]

SynTest

Test Compiler [Synopsys]

Testbench [IBM]

Vera / NTB [Synopsys]

Fast Scan [Mentor Graphics]

Logic BIST

LBIST Architect [Mentor Graphics]

Memory BIST

MBIST Architect [Mentor Graphics]

Boundary Scan Insertion

BSD Architect [Mentor Graphics]

STA - Static Timing Analysis

PrimeTime [Synopsys]

Showtime [Sequence]

Design Time [Synopsys]

CoolTime [Sequence]

Pearl [Cadence]

Transistor Level Analysis & Verification

PathMill [Synopsys]

BACKEND Flow
Hierarchical Design Planning

upiterXT [Synopsys]

PKS [Cadence]

First Encounter (FE) [Cadence]

BlastPlan [Magma]

Place & Route

Apollo/Astro [Synopsys]

IC Compiler [Synopsys]

Pinnacle / Olympus-SoC [Mentor]

<> - [Atop Tech]

Physical Compiler [Synopsys]

Gate/Silicon Ensemble [Cadence]

First Encounter/Nano Encounter [Cadence]

SoC Encounter [Cadence]

Blast Fusion [Magma]

Montery Dolphin (placer acquired by Synopsys)

AutoCells [Mentor Graphics]

Clock Tree Synthesis (CTS)

CTGen [Cadence]

Clock Tree Compiler (CTC) [Synopsys] #

Astro/Apollo/ICC [Synopsys]

Physical Verification [DRC/LVS/ERC/OPC]

Calibre [Mentor]

Hercules [Synopsys]

Assura [Cadence]

Dracula [Cadence]

Vampire [Cadence]

Diva [Cadence]

Mojave [MAGMA (Mojave)]

Parasitics/RC Extraction

Star-RCXT [Synopsys]

Arcadia [Synopsys]

Columbus Turbo [Sequence : RC Extraction]

Columbus Gold [Sequence : RLC Extraction]

Fire&Ice [earlier called as Simplex]

CalibreRC [Mentor]

Power Analysis

RTL/Gate Power Analysis

PowerTheater Analyst [Sequence : predicts rtl and netlist power] * earlier known as Sente Wattwatcher

Power Compiler [Synopsys]

PrimePower [Synopsys]

AstroRail - Static [Synopsys]

PrimeRail - Dynamic & Static [Synopsys]

Power Compiler [Synopsys]

Signal Integrity / Crosstalk

PrimeTime SI [Synopsys]

AstroXtalk [Synopsys]

CeltIC [Cadence]

Physical Studio [Sequence]

Glitch Analysis

Physical Studio [Sequence]

PTSI/PrimePower [Synopsys]

Electro Migration (EM Analysis)

Prime-Rail [Synopsys]

AstroXtalk (EM) [Synopsys]

Analog/Mixed Signal Simulation [Tr. Level]

HSPICE [Synopsys]

Nanosim [Synopsys]

HSIM [Synopsys]

Spectre [Cadence]

X-Eldo [Mentor]

Win-SPICE [Free Tool]

Columbus RF [Sequence : RLC Extraction - Analog]

B2SPICE [Beige Bag]

ngspice [open source, gEDA]

Pattern Conversion to Hardware Test

TSSI Advantest Wavebridge

TDS6000 [IBM]

IC Packaging

Foundry Flow

OPC/FAB Process

Tauras [Synopsys]

CATS [Synopsys]

Calibre OPC / RET / MDP [Mentor Graphics]

Mask Verification
Tape-Out (Post Silicon)

Source: http://groups.yahoo.com/group/VLSICore

VLSI Core - IC Design Technology Experts

Mentor Graphics User2User Conference 2011 - Bangalore - 02 Dec 2011

IC Design EDA Tools & Software

Cypress-ARM: CORTEX-M3 PSoC 5 Design Challenge

EDA Tech Forum - 2010 - Bangalore & New Delhi (India)

Gary Smith EDA market statistics 2010: Summary

Gary Smith EDA market statistics 2010: Summary

ESC Silicon Valley - San Jose, CA (April 26-29, 2010)

How to Search & Replace in 2GB Big Text File?

3D Field Solvers can be Fast - Daniel Payne

23rd International VLSI Conference (2010) - January 3-7, 2010 - Bangalore India

DipTrace - Advanced PCB Layout Software

DipTrace provides the following features:

Mentor Graphics: User2User India (U2U) - 04 December 2009, Bangalore

USER2USER 2009

Apache Design Solutions Acquires Sequence Design

100 Keyboard Shortcuts

IEEE 1801: UPF achieves formal standardisation as IEEE-1801

Application engineers (EDN Blog)

Application engineers

Oasys Design Systems- RealTime Designer - Multi-Million Gate RTL Synthesis

VLSI Conference - Call for papers - January 3-7, 2010

Runtime Design Automation - FlowTracer

EDA Utilities by Eng Han

VLSI Video Lectures from NPTEL (from IIT/IISc)

Fedora Electronic Lab (FEL)

Fedora Electronic Lab

Introduction

Featured Applications

Digital Simulation

VLSI Layout and Verification

RTL and logic synthesis design flows

Circuit Simulation

PCB Layout and Circuit Design

Micro Controller (µC) Programming and Embedded Systems Development

What is Fedora

Technical Support

History

Glossary

Editor - Emacs Learning Curve

PowerDRC/LVS - Physical Verification from Polyteda

Atoptech - APRISA - Place & Route

FireBolt - Digital IC Thermal Analysis

- Digital IC Thermal Analysis

Toped - IC Layout Editor

Quick links

Contributing

Free 45nm Open Source Digital Cell Library - Nangate

Book: Processor Design: System-On-Chip Computing for ASICs and FPGAs

Processor Design: System-On-Chip Computing for ASICs and FPGAs

What Every RF Engineer Should Know: RFID

Intro to low-power design

Code and Functional Coverage - Why Both?

ASIC Verification - Why?

Why ASIC Verification??

22nd International Conference on VLSI Design & 8th International Conference on Embedded Systems

International Conference on VLSI and Communication (2009)

Design, Automation and Test in Europe (DATE 2009)

Magma - Blast Fusion

Olympus-SoC (Place & Route System)

PrimeTime (PT) - Static Timing Analysis

RF Tools - Design & Analysis

RF Design TOOLS

List of Achronyms in VLSI

IBM: ASIC Design & Testing

SoC EDA Tools