tag:blogger.com,1999:blog-27568120746211874522024-03-06T02:14:51.575-08:00VLSI Core - IC Design Technology ExpertsWelcome to VLSICore,
It deals with VLSI design on SoC / ASIC / FPGA design flows.Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.comBlogger47125tag:blogger.com,1999:blog-2756812074621187452.post-11248792575231870652013-04-24T00:00:00.000-07:002013-04-24T00:00:14.451-07:00Understanding the FinFET process<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: center;">
<b><span style="font-size: large;">Understanding the FinFET process</span></b></div>
<div style="text-align: center;">
(Courtesy: ThresholdSystems)</div>
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Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com7tag:blogger.com,1999:blog-2756812074621187452.post-46903288120674186782013-04-23T00:00:00.000-07:002013-04-23T00:00:03.804-07:00FinFET for Dummies by Andrea Colognese<div dir="ltr" style="text-align: left;" trbidi="on">
<br />
<h2 id="post-55">
FinFET Technology for Dummies (like me)<small> </small></h2>
<h2 id="post-55">
<span style="font-size: x-small;">March 20, 2013 </span>
</h2>
<br />
finFET seems to be the most promising and disruptive technology at
the moment able to mantain the Moore’s Law trend and expectations. The
most active players (IDM, Foundries, EDA companies and IP providers) in
the semiconductor market are putting a lot of effort, investments and
emphasis on this hot topic.<br />
<br />
<b>Read more</b> here: <a href="http://cologneseandrea.wordpress.com/2013/03/20/finfet-technology-for-dummies-like-me/">http://cologneseandrea.wordpress.com/2013/03/20/finfet-technology-for-dummies-like-me/</a><br />
<b>Courtesy</b>: <a href="http://about.me/andrea.colognese" target="_blank">Andrea Colognese</a> <br />
</div>
Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com3tag:blogger.com,1999:blog-2756812074621187452.post-48555926769976805772013-04-22T01:33:00.002-07:002013-04-22T02:27:39.933-07:00An introduction to FD-SOI<div dir="ltr" style="text-align: left;" trbidi="on">
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<div style="text-align: center;">
<span style="font-size: large;">An introduction to FD-SoI </span></div>
<div style="text-align: center;">
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<div style="text-align: center;">
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Source:<span class="video-thumb yt-thumb yt-thumb-48"><span class="yt-thumb-square"><span class="yt-thumb-clip"><span class="yt-thumb-clip-inner"></span></span></span></span><br />
<span class="video-thumb yt-thumb yt-thumb-48"><span class="yt-thumb-square"><span class="yt-thumb-clip"><span class="yt-thumb-clip-inner"><img alt="STonlineMedia" src="http://i3.ytimg.com/i/jnmZw3h4XnpK3e5D2jvIGA/1.jpg?v=506c3682" width="48" /></span></span></span></span> </div>
Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com2tag:blogger.com,1999:blog-2756812074621187452.post-82011484051346009522012-08-08T00:58:00.001-07:002012-08-08T00:58:16.651-07:00AMD: OpenCL - Heterogeneous Computing<div dir="ltr" style="text-align: left;" trbidi="on">
<br />
OpenCL, Heterogeneous Computing - Lot more to learn, work and enhance today's computation needs.<br />
<br />
Visit AMD Developer Zone - India website for more details.<br />
SDK, Open Source Kits, Demos and other materials including Jobs information.<br />
<br />
<br />
<img alt="OpenCL Zone" src="http://developer.amd.com/zones/OpenCLZone/PublishingImages/new_opencl_bannerV2.jpg" style="border: 1px solid rgb(238, 238, 238);" /><br />
<br />
<br />
OpenCL™ (<strong>Open</strong> <strong>C</strong>omputing <strong>L</strong>anguage)
is the first truly open and royalty-free programming standard for
general-purpose computations on heterogeneous systems. OpenCL™ allows
programmers to preserve their expensive source code investment and
easily target multi-core CPUs, GPUs, and the new APUs.<br />
<img alt="ATI Stream" src="http://developer.amd.com/zones/OpenCLZone/PublishingImages/ati_stream_banner.JPG" />
Developed in an open standards committee with
representatives from major industry vendors, OpenCL™ gives users what
they have been demanding: a cross-vendor, non-proprietary solution for
accelerating their applications on CPU, GPUs and APUs.<br />
AMD, an early supporter of OpenCL™, and leading innovator
and provider of high-performance CPUs and GPUs, is uniquely positioned
in this industry to offer a complete acceleration platform for OpenCL™.<br />
Developer and technology partners have created several
applications, libraries and technology demonstrations taking advantage
of AMD Accelerated Parallel Processing (APP)-acceleration. These
applications and demonstrations showcase how AMD APP technology and
OpenCL™ can help improve performance and overall computational
efficiency: <br />
<ul>
<li><a href="http://developer.amd.com/sdks/AMDAPPSDK/samples/showcase/Pages/default.aspx" target="_blank" title="Link opens in new window.">AMD APP Developer Showcase </a></li>
</ul>
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<div class="pageTitle">
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University Courses Offered in India
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<span id="ctl00_PlaceHolderMain_siteMapPath"><a href="http://developer.amd.com/zones/IndiaZone/India%20University%20Programs/Pages/default.aspx#ctl00_PlaceHolderMain_siteMapPath_SkipLink"><img alt="Skip Navigation Links" height="0" src="http://developer.amd.com/WebResource.axd?d=_ttO-kr3w2EUGBya0gM1ASEg_X6pTaDytE3JemYXvdq53zVBexPEKAfceqcvSaVxh9FAt0SdzKC5k40nyEjRv8zwUek1&t=634210184576316535" style="border-width: 0px;" width="0" /></a><span><a class="breadcrumb" href="http://developer.amd.com/pages/default.aspx">Home</a></span><span> > </span><span><a class="breadcrumb" href="http://developer.amd.com/zones/Pages/default.aspx" title="AMD Developer Central Technology Zones">Zones</a></span><span> > </span><span><a class="breadcrumb" href="http://developer.amd.com/zones/IndiaZone/Pages/default.aspx">India Developer Zone</a></span><span> > </span><span class="breadcrumbCurrent">India University Programs<br />
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<img alt="" src="http://developer.amd.com/zones/IndiaZone/PublishingImages/courses_bnr_v2.jpg" style="height: 150px; width: 570px;" /><br />
A number of educational institutions now offer courses in OpenCL
programming to help prepare developers for the new era of heterogeneous
computing.<br />
Do you teach any of the heterogeneous computing technologies like,
OpenCL, C++ AMP or APARAPI? Drop us an email at: India DOT dev AT amd
DOT com and we will list it here.<br />
</div>
<h3>
Heterogeneous computing Jobs in India</h3>
Following are the companies looking for engineers who know
Heterogeneous computing languages like OpenCL for their team. Please go
to their website for more details and tell them that we send you!<br />
If you plan to hire engineers and engineering managers who have
OpenCL and C++ AMP backgrounds to work with in your company. Drop us an
email at: India DOT dev AT amd DOT com and we will list it here.<br />
<ul>
<li>AMD is hiring for engineers and engineering managers who have
OpenCL and C++ AMP backgrounds to work with our growing list of
heterogeneous computing software partners.
<ul class="linkList">
<li><a href="http://developer.amd.com/zones/IndiaZone/pages/HCJobs.aspx">Learn more</a> </li>
</ul>
</li>
<li>Samsung is looking for an engineer who knows OpenCL to work in their mobile team. The position is located in Bangalore.
<ul class="linkList">
<li><a href="http://www.samsungindiasoft.com/career_opportunities.html">Learn more</a> </li>
</ul>
</li>
<li>Siemens is looking for a Lead Research Engineer who knows OpenCL
to work in their Parallel Computing team. The position is located in
Bangalore.
<ul class="linkList">
<li><a href="https://jobsearch.siemens.biz/career?career_ns=job_listing&company=Siemens&navBarLevel=JOB_SEARCH&rcm_site_locale=en_US&career_job_req_id=82909&selected_lang=en_GB&_s.crb=9risCQOJxrZ2CqPt75kJyr6JQ9c%3d" target="_blank" title="Link opens in new window.">Learn more </a></li>
</ul>
</li>
<li>Citrix is looking for a Principal Software Dev Eng who knows
OpenCL to work in their Product Development team. The position is
located in Bangalore.
<ul class="linkList">
<li><a href="http://careers.peopleclick.com/careerscp/client_citrix/apac_region/jobDetails.do?functionName=getJobDetail&jobPostId=34255&localeCode=en-us" target="_blank" title="Link opens in new window.">Learn more</a> </li>
</ul>
</li>
</ul>
</div>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com2tag:blogger.com,1999:blog-2756812074621187452.post-848266966014005732012-08-07T23:40:00.000-07:002012-08-07T23:40:28.598-07:00FTF - Freescale Technology Forum 2012<div dir="ltr" style="text-align: left;" trbidi="on">
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<div class="ftf-mpu clearfix">
<img alt="Freescale Technology Forum 2012 - Powering Innovation" border="0" height="65" src="http://www.freescale.com/files/graphic/banner/main_pu/FTF_2012_990x105.jpg" width="640" />
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<img alt="FTF: Powering Innovation" border="0" height="77" src="http://images.freescale.com/files/graphic/other/FTF2011/4956-FTF-PwrInnvBnr-365x77-o2v1.jpg" width="340" />
<br />
<div class="intro">
Developed with the embedded ecosystem in mind, FTF's
unique environment of innovation and collaboration enables you to merge
your bright ideas with Freescale technology and power your innovations
forward.</div>
<div class="intro">
Join us at one of our upcoming global events and
experience the industry's most extensive technical training and
networking opportunities that FTF is known to deliver.</div>
<h2>
FTF 2012 Global Dates</h2>
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<table border="0" cellpadding="0" cellspacing="0" class="Tbl_a" style="width: 100%px;">
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<td class="Thw">
<a href="http://www.freescale.com/webapp/sps/site/overview.jsp?code=FTF_2012_AMERICA_HOME_CAT">
<b>FTF Americas</b>
</a>
</td>
<td class="Thw">June 18-21</td>
<td class="Thw">San Antonio, Texas</td>
</tr>
<tr>
<td class="Thg">
<a href="http://www.freescale.com/webapp/sps/site/overview.jsp?code=FTF_2012_CHINA_HOME_CAT">
<b>FTF China</b>
</a>
</td>
<td class="Thg">August 14-15</td>
<td class="Thg">Beijing</td>
</tr>
<tr>
<td class="Thw">
<a href="http://www.freescale.com/webapp/sps/site/overview.jsp?code=FTF_2012_INDIA_HOME_CAT">
<b>FTF India</b>
</a>
</td>
<td class="Thw">August 23-24</td>
<td class="Thw">Bengaluru</td>
</tr>
<tr>
<td class="Thg">
<a href="http://www.freescale.com/webapp/sps/site/overview.jsp?code=FTF_2012_JAPAN_HOME_CAT">
<b>FTF Japan</b>
</a>
</td>
<td class="Thg">October 22-23</td>
<td class="Thg">Tokyo</td>
</tr>
</tbody>
</table>
</div>
<div class="ccr verticalDotted-1" style="border: 1px solid rgb(204, 204, 204); min-height: 343px;">
<div class="market-splash">
<a href="http://www.freescale.com/webapp/sps/site/overview.jsp?code=FTF_2012_AMERICA_HOME_CAT">
<img alt="FTF Americas Content Available On-Demand" border="0" class="thumb" height="74" src="http://cache.freescale.com/files/graphic/other/FTF2012/FTF2012TN_68X74.jpg" width="68" />
</a>
</div>
<h2>
FTF Attendee Benefits</h2>
<ul class="boxes clearfix">
<li>Expand your knowledge: Access invaluable content through highly
technical training sessions, hands-on workshops and visionary keynote
speakers.</li>
<li>Elevate your embedded designs: Get hands-on inspiration with the
latest solutions from Freescale and its ecosystem partners in the
Technology Lab.</li>
<li>Connect and collaborate: Network and exchange ideas with
application engineers, product experts, peers, media, analysts and
executives.</li>
<li>Inspire your innovations: Take home the knowledge and insights to power your next bright ideas.</li>
</ul>
</div>
</div>
<div class="rc">
<div id="GlobalSponsors">
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<div class="iu">
<h1>
Training & Events</h1>
<ul>
<li><a href="http://www.freescale.com/webapp/sps/site/overview.jsp?nodeId=0ST2BDF2BF5">On-Demand Training</a></li>
<li><a href="http://www.freescale.com/webapp/sps/site/overview.jsp?nodeId=0ST2BDF2BF7">Live In-Depth Training</a></li>
<li><a href="http://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=0ST2BDF2539">Industry Events</a></li>
<li><a href="http://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=0ST2BDF3BA8">Designing with Freescale Seminar Series</a></li>
</ul>
</div>
<div class="iu">
<h1>
University Programs</h1>
<ul>
<li><strong><a href="http://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=06258A">Students and Faculty —</a></strong>
Collaborate with Freescale on the future of electronics innovation</li>
</ul>
</div>
</div>
</div>VLSICore - Technology Expertshttp://www.blogger.com/profile/11189927779337620106noreply@blogger.com4Bangalore, Karnataka, India12.9715987 77.594562712.724026199999999 77.2787057 13.2191712 77.910419699999991tag:blogger.com,1999:blog-2756812074621187452.post-51273544003877118842012-07-09T02:08:00.002-07:002012-07-09T02:08:43.521-07:00VLSID 2013 - 26th International Conference on VLSI Design 2013<div dir="ltr" style="text-align: left;" trbidi="on">
<div dir="ltr" style="font-family: "Trebuchet MS",sans-serif; text-align: left;" trbidi="on">
<a href="https://www.facebook.com/pages/VLSI-Design-Conference/407521505959054#" target="_blank"><img alt="fb" height="24" src="http://www.vlsidesignconference.org/images/fb.png" width="24" /></a> <a href="https://www.twitter.com/VLSID" target="_blank"><img alt="tweeter" height="24" src="http://www.vlsidesignconference.org/images/tweeter.png" width="24" /></a> <a href="http://www.linkedin.com/groups/Internatio-nal-Conference-on-VLSI-4107994" target="_blank"><img alt="linkedin" height="24" src="http://www.vlsidesignconference.org/images/linkedin.png" width="24" /></a><br />
<h3>
<img alt="body heading" height="13" src="http://www.vlsidesignconference.org/images/body_heading_green_technology.png" width="345" /></h3>
<div class="bodyContent">
<b>URL</b>: <a href="http://www.vlsidesignconference.org/">http://www.vlsidesignconference.org/</a><br />
<br />
This joint conference is a forum for researchers and designers
to present and discuss current topics in VLSI design, electronic design
automation, embedded systems, and enabling technologies. Two days of
tutorials will be followed by three days of regular paper sessions,
special sessions, and embedded tutorials. Industry presentation sessions
along with exhibits, panel discussions, Design Contest, and Education
Forum round off the program.<br />
<br />
The theme for the conference is Green Technology - A New Era for
Electronics, which explores the ability of VLSI and embedded circuits
and systems to positively impact the environment. Example areas under
the theme include (but are not restricted to) designing energy-efficient
VLSI circuits, improving the efficiency of energy-hungry applications
such as data centers, developing intelligent monitoring and control
systems such as smart grids, and using integrated circuits or embedded
systems to leverage novel green technologies.<br />
<br />
Pune city, also known as the Oxford of the East, has witnessed
huge growth in its VLSI and embedded community over the past few years
and is proud to host its very first VLSI Design Conference. The
conference organizing committee is looking forward to making this an
unforgettable experience for all attendees.<br />
<br /></div>
<br />
<h3>
<img alt="body heading" height="13" src="http://www.vlsidesignconference.org/images/body_heading_conference_program.png" width="151" /></h3>
<div class="bodyContent">
<table border="0" cellpadding="0" cellspacing="0" style="width: 480px;">
<tbody>
<tr>
<td class="impDates" height="23" width="34">Day 1</td>
<td class="impDates" width="10">:</td>
<td class="impDates" width="107">5th January 2013</td>
<td class="impDates" width="18">:</td>
<td class="impDates" width="311">Tutorial</td>
</tr>
<tr>
<td class="impDates" height="23">Day 2</td>
<td class="impDates">:</td>
<td class="impDates">6th January 2013</td>
<td class="impDates">:</td>
<td class="impDates">Tutorial</td>
</tr>
<tr>
<td class="impDates" height="23">Day 3</td>
<td class="impDates">:</td>
<td class="impDates">7th January 2013</td>
<td class="impDates">:</td>
<td class="impDates">Inaugural, Technical Sessions, Student </td>
</tr>
<tr>
<td class="impDates" height="23">Day 4</td>
<td class="impDates">:</td>
<td class="impDates">8th January 2013</td>
<td class="impDates">:</td>
<td class="impDates">Valedictory/Award, Technical Sessions, Student Conference</td>
</tr>
<tr>
<td class="impDates" height="23">Day 5</td>
<td class="impDates">:</td>
<td class="impDates">9th January 2013</td>
<td class="impDates">:</td>
<td class="impDates">Technical Sessions, RASDAT 2013 workshop</td>
</tr>
<tr>
<td class="impDates" height="23">Day 6</td>
<td class="impDates">:</td>
<td class="impDates">10th January 2013</td>
<td class="impDates">:</td>
<td class="impDates"> RASDAT 2013 workshop</td>
</tr>
</tbody></table>
</div>
<br />
<b>Proposal submission links now available!</b><br />
<a href="https://www.softconf.com/d/vlsi2013" target="_blank">Papers</a>, <a href="https://www.softconf.com/d/vlsi2013_tutorial" target="_blank">Tutorials</a>, <a href="https://www.softconf.com/d/vlsi2013_usertrack" target="_blank">User/designer track submissions</a>, <a href="https://www.softconf.com/d/vlsi2013_designcontest" target="_blank">Design contest</a> and <a href="https://www.softconf.com/d/vlsi2013_emb_special_panel" target="_blank">Embedded Tutorials, Special Sessions, Panels.</a> <br />
<br />
<b>Deadline for Regular Paper submission has been extended to 24th July, 2012.</b>
Please submit Tutorial, User/designer track submissions, Design contest
and Embedded Tutorials, Special sessions, Panels proposals by 2nd
August, 2012.<br />
<h3>
<img alt="body heading" height="15" src="http://www.vlsidesignconference.org/images/body_heading_important_dates.png" width="100" /></h3>
<div class="bodyContent">
<table border="0" cellpadding="0" cellspacing="0" style="width: 480px;">
<tbody>
<tr>
<td align="left" class="impDates" height="23" valign="top" width="216">Paper Submissions</td>
<td align="left" class="impDates" valign="top" width="40">:</td>
<td align="left" class="impDates" valign="top" width="224">24th July, 2012</td>
</tr>
<tr>
<td align="left" class="impDates" height="23" valign="top">Tutorial Submissions</td>
<td align="left" class="impDates" valign="top">:</td>
<td align="left" class="impDates" valign="top">2nd August, 2012</td>
</tr>
<tr>
<td align="left" class="impDates" height="23" valign="top">User/Designer Submissions</td>
<td align="left" class="impDates" valign="top">:</td>
<td align="left" class="impDates" valign="top">2nd August, 2012</td>
</tr>
<tr>
<td align="left" class="impDates" height="23" valign="top">Call for embedded tutorials, special sessions, and panels</td>
<td align="left" class="impDates" valign="top">:</td>
<td align="left" class="impDates" valign="top">2nd August, 2012</td>
</tr>
<tr>
<td align="left" class="impDates" height="23" valign="top">Design Contest Submission</td>
<td align="left" class="impDates" valign="top">:</td>
<td align="left" class="impDates" valign="top">15th September, 2012 </td>
</tr>
<tr>
<td align="left" class="impDates" height="23" valign="top">Acceptance of notification</td>
<td align="left" class="impDates" valign="top">:</td>
<td align="left" class="impDates" valign="top">7th September, 2012</td>
</tr>
<tr>
<td align="left" class="impDates" height="23" valign="top">Camera ready paper due</td>
<td align="left" class="impDates" valign="top">:</td>
<td align="left" class="impDates" valign="top">1st October, 2012</td>
</tr>
</tbody></table>
</div>
<br />
<b>URL</b>: <a href="http://www.vlsidesignconference.org/">http://www.vlsidesignconference.org/</a></div>
</div>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com4tag:blogger.com,1999:blog-2756812074621187452.post-70887034923633141372011-10-28T22:19:00.000-07:002011-11-29T22:20:36.772-08:00Mentor Graphics User2User Conference 2011 - Bangalore - 02 Dec 2011<div dir="ltr" style="text-align: left;" trbidi="on">
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<img alt="Mentor Graphics User2User - INVITATION" height="223" src="https://mail.google.com/mail/?ui=2&ik=906d6a5659&view=att&th=133f31c9a8ba9b7b&attid=0.1&disp=emb&zw" width="620" /><span style="font-size: 12.0pt;"></span></div>
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<span><span style="font-family: "Arial","sans-serif"; font-size: 11.0pt;">User2User 2011 India</span></span><br />
<br />
<span style="color: #666666; font-family: "Arial","sans-serif"; font-size: 10.0pt;">You are invited to
<a href="http://lyris.mentor-info.com/t/233490/16410881/20897/6911/" target="_blank">User2User India 2011</a>, the International Mentor Graphics user conference to be held on December 02, 2011 in Bangalore, India.</span><br />
<span style="color: #666666; font-family: "Arial","sans-serif"; font-size: 10.0pt;">Join
us for a full day of technical sessions and gain immediately-useful
knowledge in areas including Functional Verification, Silicon Test,
Design 2 Silicon and System Design.
Meet technical experts from user group of Mentor Graphics, Mentor
technical staff and see product demos, learn best practices from other
Mentor customers, and network with your colleagues. It all happens on:</span><br />
<br />
<b style="color: black;"><span style="font-family: "Arial","sans-serif"; font-size: 10pt;">Date: December 02, 2011</span></b><b><span style="color: #666666; font-family: "Arial","sans-serif"; font-size: 10.0pt;"><br />
Location: <span style="color: black;">Vivanta by Taj on MG Road</span> (formerly Taj Residency), Bangalore<br />
41/3 Mahatma Gandi Road<br />
Bangalore 560001</span></b><span style="color: #666666; font-family: "Arial","sans-serif"; font-size: 10.0pt;"></span><br />
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<span style="color: #666666; font-family: "Arial","sans-serif"; font-size: 10pt;">Don't miss out on this excellent networking and learning opportunity.</span><br />
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<span><span style="font-family: "Arial","sans-serif"; font-size: 11pt;"><a href="http://lyris.mentor-info.com/t/233490/16410881/20897/6911/" target="_blank">Register today!</a></span></span><span style="color: #666666; font-family: "Arial","sans-serif"; font-size: 10.0pt;"></span><br />
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<b><span style="color: #666666; font-family: "Arial","sans-serif"; font-size: 10pt;">Registration ends on <span style="color: red;">30 Nov, 2011</span></span></b></td></tr>
</tbody></table>
</div>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com5tag:blogger.com,1999:blog-2756812074621187452.post-6703006656425962292011-09-27T23:20:00.000-07:002011-09-28T22:17:54.822-07:00IC Design EDA Tools & Software<div>
<span style="font-family: Verdana,sans-serif;"><span style="font-size: large;"><b>EDA Tools & Software collection </span></b><p>
Thanks for your interest. Feel free to add the EDA tools/softwares for IC Design/FPGA that you are aware of.<br>
Visit the EDA Tools collection page <a target="_blank" href="http://vlsi-core.blogspot.com/2008/07/soc-eda-tools.html"><b>here</b></a>.<p>
Added EDA Tools/Software will be reviewed & updated to a new page soon.<br>
Thanks for your help to keep this list up to date.<br>
</span><br />
<iframe src="https://docs.google.com/spreadsheet/embeddedform?formkey=dEM4d092Sm5iTTN6U1FXMmdXTFRoeUE6MQ" width="100%" height="2948" frameborder="0" marginheight="0" marginwidth="0">Loading...</iframe>
</div>
Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com3tag:blogger.com,1999:blog-2756812074621187452.post-78286136795995861482011-01-19T01:34:00.001-08:002011-01-19T01:36:34.618-08:00Cypress-ARM: CORTEX-M3 PSoC 5 Design Challenge<p><img style="width: 487px; height: 111px;" src="http://www.cypress.com/fckimages/headerimage.jpg" alt="" /> <span style=";font-family:Arial,san-serif;font-size:85%;" > <p><b>Join the ARM-PSoC Design Challenge With $10,000 in Cash and Prizes</b></p> <p style="color: rgb(255, 102, 0);"><b>Deadline extended to January 24<sup>th</sup>.</b></p> <ul><li>Want to put your ARM and PSoC design skills up against those of your peers?</li><br /><li>Want to present your design directly to Cypress CEO T.J. Rodgers and Cypress’s executive staff?</li><br /><li>Want to comment on your peers’ PSoC designs, holding power over whether their designs get time<br /> in the industry spotlight from Cypress and <i>EE Times</i>?</li><br /></ul> <p align="justify">Check out the ARM® Cortex™M3/PSoC 5 Design Challenge, a test of design skill geared to determine the<br />most innovative and useful designs for the Cypress PSoC 5 architecture. The PSoC 5 solution is powered by<br />the ARM Cortex-M3 processor.</p> <p align="justify">Prizes awarded for top designs, best video and community choice as well as community members who<br />participate in the forums or provide ratings on design entries.</p> <p>Visit <a href="http://www.cypress.com/go/challenge" target="_blank">www.cypress.com/go/challenge</a> now to check out the contest and enter your design.</p> </span> <a href="http://www.cypress.com/go/challenge" target="_blank"><img src="http://www.cypress.com/fckimages/footerimage.gif" alt="" border="0" height="80" width="200" /></a></p> <img style="width: 455px; height: 74px;" src="http://download.cypress.com/newsletter/images/Footer.png" border="0" /><br /><br />Source: Cypress NewsletterAnenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-31989471340839061812010-07-28T23:14:00.000-07:002010-07-28T23:18:02.226-07:00EDA Tech Forum - 2010 - Bangalore & New Delhi (India)<table style="width: 558px; height: 802px;" class="MsoNormalTable" border="0" cellpadding="0" cellspacing="0"> <tbody> <tr align="center"> <td style="padding: 0.75pt;" colspan="2"> <p style="margin-bottom: 12pt;" class="MsoNormal"><a name="toc_31651"></a><a title="http://lyris.mentor-info.com/t/175412/950596/15785/3762/" href="http://lyris.mentor-info.com/t/175412/950596/15785/3762/" target="_blank"><span style="text-decoration: none;" title="http://lyris.mentor-info.com/t/175412/950596/15785/3762/"><img style="width: 414px; height: 62px;" id="_x0000_i1025" title="http://lyris.mentor-info.com/t/175412/950596/15785/3762/" alt="EDA Tech Forum India" src="http://images.mentor.com/email/edatf10emailindia.jpg" border="0" /></span></a></p></td></tr> <tr> <td style="border-width: medium 1pt medium medium; border-style: none solid none none; border-color: -moz-use-text-color rgb(234, 234, 234) -moz-use-text-color -moz-use-text-color; padding: 0.75pt; width: 6.25in;" valign="top" width="600"> <table style="width: 436px; height: 726px;" class="MsoNormalTable" border="0" cellpadding="0" cellspacing="0"> <tbody> <tr> <td style="padding: 7.5pt;"> <p class="MsoNormal"><strong><span style="font-family: 'Arial','sans-serif'; color: rgb(94, 159, 194);">EDA TECH FORUM INDIA</span></strong><b><span style="font-family: 'Arial','sans-serif'; color: rgb(94, 159, 194);"><br /><strong><span style="font-family: 'Arial','sans-serif';">Delivering the Latest in 10X Design Improvements </span></strong></span></b><b><span style="font-family: 'Arial','sans-serif'; color: rgb(102, 102, 102); font-size: 10pt;"><br /><br /><strong><span style="font-family: 'Arial','sans-serif';">Two Locations:</span></strong><br /><strong><span style="font-family: 'Arial','sans-serif';"><a title="http://lyris.mentor-info.com/t/175412/950596/15783/4933/" href="http://lyris.mentor-info.com/t/175412/950596/15783/4933/">Bangalore</a>- Wednesday, August 18, 2010</span></strong><br /><strong><span style="font-family: 'Arial','sans-serif';"><a title="http://lyris.mentor-info.com/t/175412/950596/15784/4934/" href="http://lyris.mentor-info.com/t/175412/950596/15784/4934/" target="_blank">New Deli</a> - Friday, August 20, 2010</span></strong><br /><strong><span style="font-family: 'Arial','sans-serif';">8:00 – 17:50</span></strong></span></b><span style="font-family: 'Arial','sans-serif'; color: rgb(102, 102, 102); font-size: 10pt;"> <br /><br />Join other EE designers and engineers at one of two complimentary EDA Tech Forums in India - <strong><span style="font-family: 'Arial','sans-serif';"><a title="http://lyris.mentor-info.com/t/175412/950596/15783/4933/" href="http://lyris.mentor-info.com/t/175412/950596/15783/4933/" target="_blank">Bangalore</a></span></strong> and <strong><span style="font-family: 'Arial','sans-serif';"><a title="http://lyris.mentor-info.com/t/175412/950596/15784/4934/" href="http://lyris.mentor-info.com/t/175412/950596/15784/4934/" target="_blank">New Delhi</a></span></strong>. This year's event series features a new lineup of speakers, sponsors, and technology tracks in a one-day event that provides an excellent mix of educational and networking opportunities. <br /><br /><strong><span style="font-family: 'Arial','sans-serif';">Create your personal agenda with tracks in:</span></strong> </span></p> <ul type="disc"><li style="color: rgb(102, 102, 102);" class="MsoNormal"><span style="font-family: 'Arial','sans-serif'; font-size: 10pt;">Maximizing Front-end Design: From ESL through RTL</span> </li><li style="color: rgb(102, 102, 102);" class="MsoNormal"><span style="font-family: 'Arial','sans-serif'; font-size: 10pt;">Accelerate Time to Manufacturing</span> </li><li style="color: rgb(102, 102, 102);" class="MsoNormal"><span style="font-family: 'Arial','sans-serif'; font-size: 10pt;">Increase Productivity in System-level Design</span> </li><li style="color: rgb(102, 102, 102);" class="MsoNormal"><span style="font-family: 'Arial','sans-serif'; font-size: 10pt;">Innovations in Embedded Software and User Interface Development</span> </li></ul> <p><span style="font-family: 'Arial','sans-serif'; color: rgb(102, 102, 102); font-size: 10pt;">Start the day with exciting keynote speakers, like <b>Pamela Kumar of IBM</b>, <b>Manjunath Hebbar of HCL Technologies</b>, and <b>Pravin Madhani of Mentor Graphics</b> as he discusses how in the next five years, 10X improvements in design methodologies are needed. After attending in-depth technical breakout sessions, there will also be plenty of time to meet with leading EDA solution providers in the multi-vendor fair.</span></p> <p class="MsoNormal"><strong><span style="font-family: 'Arial','sans-serif'; color: rgb(102, 102, 102); font-size: 10pt;">Event Highlights:</span></strong><span style="font-family: 'Arial','sans-serif'; color: rgb(102, 102, 102); font-size: 10pt;"> </span></p> <ul type="disc"><li style="color: rgb(102, 102, 102);" class="MsoNormal"><span style="font-family: 'Arial','sans-serif'; font-size: 10pt;">Attend in-depth technical sessions from sponsors</span> </li><li style="color: rgb(102, 102, 102);" class="MsoNormal"><span style="font-family: 'Arial','sans-serif'; font-size: 10pt;">Test drive new tools from EDA solution providers at the multi-vendor fair</span> </li><li style="color: rgb(102, 102, 102);" class="MsoNormal"><span style="font-family: 'Arial','sans-serif'; font-size: 10pt;">Enjoy great food and win prizes while you network with fellow EE designers</span> </li></ul> <p><span style="font-family: 'Arial','sans-serif'; color: rgb(102, 102, 102); font-size: 10pt;">Guarantee your participation at the EDA Tech Forum. Register today.</span></p> <table style="background: none repeat scroll 0% 0% rgb(94, 159, 194);" class="MsoNormalTable" border="0" cellpadding="0" cellspacing="0"> <tbody> <tr> <td style="padding: 1.5pt;"> <div align="center"> <table style="background: none repeat scroll 0% 0% white;" class="MsoNormalTable" border="0" cellpadding="0" cellspacing="1"> <tbody> <tr> <td style="padding: 3.75pt; width: 100%; background: none repeat scroll 0% 0% rgb(94, 159, 194);" width="100%"> <p style="text-align: center;" class="MsoNormal" align="center"><a title="http://lyris.mentor-info.com/t/175412/950596/15783/4933/" href="http://lyris.mentor-info.com/t/175412/950596/15783/4933/" target="_blank"><span style="font-family: 'Arial','sans-serif'; color: white; font-size: 7.5pt; text-decoration: none;" title="http://lyris.mentor-info.com/t/175412/950596/15783/4933/">REGISTER NOW - Bangalore</span></a> </p></td></tr></tbody></table></div></td></tr></tbody></table> <p style="margin-bottom: 12pt;" class="MsoNormal"><span style="font-family: 'Arial','sans-serif'; color: rgb(102, 102, 102); font-size: 10pt;"> </span></p> <table style="background: none repeat scroll 0% 0% rgb(94, 159, 194);" class="MsoNormalTable" border="0" cellpadding="0" cellspacing="0"> <tbody> <tr> <td style="padding: 1.5pt;"> <div align="center"> <table style="background: none repeat scroll 0% 0% white;" class="MsoNormalTable" border="0" cellpadding="0" cellspacing="1"> <tbody> <tr> <td style="padding: 3.75pt; width: 100%; background: none repeat scroll 0% 0% rgb(94, 159, 194);" width="100%"> <p style="text-align: center;" class="MsoNormal" align="center"><a title="http://lyris.mentor-info.com/t/175412/950596/15784/4934/" href="http://lyris.mentor-info.com/t/175412/950596/15784/4934/" target="_blank"><span style="font-family: 'Arial','sans-serif'; color: white; font-size: 7.5pt; text-decoration: none;" title="http://lyris.mentor-info.com/t/175412/950596/15784/4934/">REGISTER NOW - New Delhi</span></a> </p></td></tr></tbody></table></div></td></tr></tbody></table></td></tr></tbody></table></td></tr></tbody></table>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-54338085121025206942010-07-23T03:20:00.000-07:002010-07-23T03:25:18.878-07:00Gary Smith EDA market statistics 2010: Summary<h1>Gary Smith EDA market statistics 2010: Summary</h1> <span id="ContentBody"> <p><strong>(July 22, 2010) -- </strong>These market statistics were compiled by Nancy Wu & Mary Olsson, part of the Gary Smith EDA team. The biggest change in 2009 was Mentor passing Cadence to become number two in product sales in EDA. This is an indication of the market shift caused by the move into the ESL Methodology. <span style="font-weight: bold;">Synopsys remains a strong number one</span>.</p><p><span style="font-weight: bold;">Mentor also grabbed #2</span> overall in IC design. With the acquisition of Valor, Mentor is also now 3× as large as its next competitor in PCB design.</p><p>We believe that the recent changes in Cadence has stopped their market share decline, similar to the changes made at Mentor, bringing in Walden Rhines, during the switch to the RTL design methodology.</p><p>Read more to know the statistics report - <a href="http://www.electroiq.com/index/display/article-display/5557931648/articles/solid-state-technology/semiconductors/industry-news/technology-news/2010/july/gary-smith_eda_market.html">Click Here</a><br /></p><p>Source: This article is from <a target="_blank" href="http://www.electroiq.com/index/Semiconductors.html">Solid State Technology</a></p></span><div class="contentsrcdisplay"> </div>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-22764931336423504862010-03-11T23:09:00.000-08:002010-03-11T23:11:25.683-08:00ESC Silicon Valley - San Jose, CA (April 26-29, 2010)More info. & Register : <a href="http://bit.ly/esc4sj" target="_blank" rel="nofollow" onmousedown="'UntrustedLink.bootstrap($(this),">http://bit.ly/esc4sj</a><br /><br /><span style="font-weight: bold;">ESC Silicon Valley - San Jose, CA (April 26-29, 2010)</span><br /><br />Attend the next ESC which brings together system architects, design engineers, suppliers, analysts and media from across the globe. With 10,000 total attendees, it’s the largest and most prestigious annual engineering event in America. Participate in ESC, and you will meet with your customers, renew relationships, sell to pro...spects, attend press meetings, make announcements, and talk to partners – Only at ESC.<br /><br />Keynote Speakers:<br /><br />Dr. Michio Kaku<br />Theoretical Physicist, Bestselling Author and Science Popularizer<br /><br />Richard Templeton<br />Chairman, President, Chief Executive Officer, Texas Instruments<br /><br />Jason Wolf<br />Vice President, North America, Better Place<br /><br /><ul><li> <strong><a href="http://esc-sv.techinsightsevents.com/sessions_by_track#3">Designing with Open-Source Software, including Linux and Android</a></strong></li><li> <strong><a href="http://esc-sv.techinsightsevents.com/sessions_by_track#4">Developing for Windows Embedded</a></strong></li><li> <strong><a href="http://esc-sv.techinsightsevents.com/sessions_by_track#9">Microprocessors/Microcontrollers/DSPs</a> </strong></li><li><strong> <strong><a href="http://esc-sv.techinsightsevents.com/sessions_by_track#12">Networking and Connectivity</a></strong></strong></li><li><strong> <strong><a href="http://esc-sv.techinsightsevents.com/sessions_by_track#13">Operating System Selections, Tips and Tricks</a></strong></strong></li></ul>More info. & Register : <a href="http://bit.ly/esc4s" target="_blank" rel="nofollow" onmousedown="'UntrustedLink.bootstrap($(this),">http://bit.ly/esc4s</a>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-91062391000434076982010-03-10T00:56:00.000-08:002010-03-10T01:12:57.588-08:00How to Search & Replace in 2GB Big Text File?<span style="font-weight: bold;font-family:trebuchet ms;" >Problem Statement</span><span style="font-family:trebuchet ms;">:</span><hr><blockquote style="font-family:trebuchet ms;"><div>I am trying to edit few lines in a file, but it is a very big file more than 2GB text file. Opening, editing and saving in vi editor takes a long time.</div> <div><br /></div><div style="font-weight: bold;"><div>1. To search and replace a string 'STRING' in a big file.</div><div><br /></div></div><div style="font-weight: bold;">2. To find few lines having string 'GROUPS' and remove them from the original file.I tried 'grep -v 'GROUPS' file > newfile', is there any better way than this.</div><div><br /></div><div>Is this possible to do without opening a file through other ways not in Vi editor.</div></blockquote><hr><blockquote face="trebuchet ms"><span style="font-weight: bold;">Perl Solution</span><br /><pre style="color: rgb(51, 51, 255); font-weight: bold; font-family: trebuchet ms;"> perl -e 's/gopher/World Wide Web/gi' -p -i.bak *.html</pre> <p>This command, issued at the Unix prompt, executes the short Perl program specified in single quotes. This program consists of one Perl operation: it substitutes for original word "gopher" the phrase "World Wide Web" (<b>g</b>lobally, <b>i</b>gnoring case). The command line options imply that the Perl program should run for each file ending in <code>.html</code> in the current directory. If any file <code>blah.html</code> needs changing, a backup of the original is made as file <code>blah.html.bak</code>.�</p><br />For more info on perl, please go through<br /><a href="http://www.cs.tut.fi/%7Ejkorpela/perl/course.html#whatis" target="_blank">http://www.cs.tut.fi/~jkorpela/perl/course.html#whatis</a><br /></blockquote><hr><blockquote style="font-family: trebuchet ms;"><span style="font-weight: bold;">sed solution</span>:<br />for deleting GROUPS from all lines<br />use this :<br /><span style="color: rgb(51, 51, 255); font-weight: bold;">sed -i '/GROUPS/d' file_name</span><br />OR<br /><span xmlns="http://www.w3.org/2001/XInclude" class="example"><span style="color: rgb(51, 51, 255); font-weight: bold;">sed 's/old_string/new_string/g' oldfilename > newfilename</span><br /></span><br /></blockquote><hr><span style="font-weight: bold;font-family:trebuchet ms;" >Source</span><span style="font-family:trebuchet ms;">: </span><a style="font-weight: bold; font-family: trebuchet ms;" target="_blank" href="http://groups.yahoo.com/group/VLSICore/join">VLSICore</a><span style="font-family:trebuchet ms;"> Members</span>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-27644355298940457222009-12-10T02:33:00.000-08:002009-12-10T02:36:21.258-08:003D Field Solvers can be Fast - Daniel Payne3D Field Solvers can be Fast<br />by <a href="http://www.chipdesignmag.com/payne/author/admin/" title="Posts by Daniel Payne">Daniel Payne</a> in <a href="http://www.chipdesignmag.com/payne/category/extraction-tools/" title="View all posts in Extraction tools" rel="category tag">Extraction tools</a> <p>In SoC designs today parasitic extraction tools produce RC and sometimes L or S-parameter values for full-chip designs using either pattern-matching or equation-based techniques. It gets the job done for most digital designs however when you really need accuracy in your parasitics then you must consider something more accurate, namely a 3D field solver.</p><p><a href="http://www.chipdesignmag.com/payne/2009/12/09/3d-field-solvers-can-be-fast/">Read more...</a></p><p><span style="font-weight: bold;">Source</span>: <a href="http://www.chipdesignmag.com/payne/2009/12/09/3d-field-solvers-can-be-fast/">http://www.chipdesignmag.com/payne/2009/12/09/3d-field-solvers-can-be-fast/</a><br /></p>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-38959671920198075352009-11-21T10:31:00.000-08:002009-12-01T10:42:19.756-08:0023rd International VLSI Conference (2010) - January 3-7, 2010 - Bangalore India<table style="width: 403px; height: 60px; text-align: left; margin-left: auto; margin-right: auto;" border="0" cellpadding="0" cellspacing="0"><tbody><tr><td style="text-align: right;" valign="top" width="390"><img style="width: 260px; height: 64px;" src="http://vlsiconference.com/vlsi2010/images/top-1vlsi.gif" alt="VLSI Design 2010" title="VLSI Design 2010" /></td> <td style="text-align: left;" valign="top"><img style="width: 242px; height: 64px;" src="http://vlsiconference.com/vlsi2010/images/top-2embedded.gif" alt="VLSI Design 2010" title="VLSI Design 2010" /></td> </tr> <tr> <td style="text-align: right;" valign="top"><img style="width: 259px; height: 31px;" src="http://vlsiconference.com/vlsi2010/images/4th-title.gif" alt="VLSI Design 2010" title="VLSI Design 2010" /></td> <td style="text-align: left;" valign="top"><img style="width: 242px; height: 31px;" src="http://vlsiconference.com/vlsi2010/images/4th-title1.gif" alt="VLSI Design 2010" title="VLSI Design 2010" /></td></tr></tbody></table><br /><br /><div style="text-align: center;"><img src="http://vlsiconference.com/vlsi2010/images/theme-VLSI.gif" alt="THEME: Affordable Technology for Emerging Markets" title="THEME: Affordable Technology for Emerging Markets" height="58" width="416" /> </div><p style="text-align: center;">This joint conference is a forum for researchers and designers to present and discuss various aspects of VLSI design, electronic design automation (EDA), enabling technologies, and embedded systems. It covers the entire spectrum of activities in the two vital areas of very large scale integration (VLSI) and embedded systems, which underpin the semiconductor industry. The five-day technical program will consist of three days of regular paper sessions, special sessions, embedded tutorials, industry presentation sessions, panel discussions, design contests and industrial exhibits, and two days of full-day tutorials.</p><div style="text-align: center;"> Electronic systems are ubiquitous today in multiple applications, with emerging markets in health-care, entertainment and machine intelligence spurring several new ones. These markets often hinge delicately on the right blend of technology and affordability. Accordingly, the theme for this conference is set as “Affordable Technology for Emerging Markets”.<br /><br /><table style="text-align: left; margin-left: auto; margin-right: auto;" border="0" cellpadding="0" cellspacing="0" width="396"><tbody><tr><td style="font-weight: bold;" class="CPtitle" align="left" height="30" valign="top" width="198">Tutorials</td> <td style="font-weight: bold;" class="CPtitle" align="left" valign="top">Conference</td> </tr> <tr> <td align="left" height="26" valign="middle"><a href="http://vlsiconference.com/vlsi2010/conference-tutorials.html" class="link_menu_blue1">Day 1: Sunday January 3, 2010</a></td> <td align="left" valign="middle"><a href="http://vlsiconference.com/vlsi2010/conference-program.htm" class="link_menu_blue1">Day 1: Tuesday January 5, 2010</a></td> </tr> <tr> <td align="left" height="26" valign="middle"><a href="http://vlsiconference.com/vlsi2010/conference-tutorials-2.html" class="link_menu_blue1">Day 2: Monday January 4, 2010</a></td> <td align="left" valign="middle"><a href="http://vlsiconference.com/vlsi2010/conference-program2.html" class="link_menu_blue1">Day 2: Wednesday January 6, 2010</a></td> </tr> <tr> <td align="left" height="26" valign="middle"><img src="http://vlsiconference.com/vlsi2010/images/spacer.gif" alt="" height="1" width="1" /></td> <td align="left" valign="middle"><a href="http://vlsiconference.com/vlsi2010/conference-program3.html" class="link_menu_blue1">Day 3: Thursday January 7, 2010</a></td></tr></tbody></table><br /></div><table style="text-align: left; margin-left: auto; margin-right: auto;" border="0" cellpadding="4" cellspacing="1" width="417"><tbody><tr align="center" valign="middle"><td colspan="3" class="form6" background="images/call-forpaper-bg.gif" height="30">IMPORTANT DATES</td> </tr> <tr valign="middle"> <td class="form22" align="left" height="20" width="292">Fellowship Notification</td> <td class="form22" align="left" height="20" width="3">:</td> <td class="form5" align="left" height="20" width="166">Nov. 16<sup>th</sup>, 2009</td> </tr> <tr valign="middle"> <td class="form22" align="left" height="20">Registration (Early bird rates)</td> <td class="form22" align="left" height="20">:</td> <td class="form5" align="left" height="20">Dec. 7<sup>th</sup>, 2009</td> </tr> <tr valign="middle"> <td class="form22" align="left" height="20">Exhibits (Early bird rates)</td> <td class="form22" align="left" height="20">:</td> <td class="form5" align="left" height="20">Dec. 7<sup>th</sup>, 2009</td></tr></tbody></table><br />Links: <a href="http://vlsiconference.com/vlsi2010/">http://vlsiconference.com/vlsi2010/</a>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-5710740684014807682009-11-18T10:47:00.000-08:002009-12-01T10:55:53.700-08:00DipTrace - Advanced PCB Layout Software<div style="text-align: center;"><a href="http://www.diptrace.com/"><img src="http://diptrace.com/img/logo_2.gif" border="0" /></a><br /></div><p style="font-weight: bold; text-align: center;">DipTrace Free – 1.30</p><p>DipTrace is an advanced PCB design software application that consists of 4 modules: PCB Layout with efficient auto-router, Schematic Capture, Component and Pattern Editors that allow you to design your own component libraries. Besides being very simple to learn, which is quite an accomplishment for a PCB design software package, this solution has a very intuitive user interface and many innovative features. For instance, a schematic can be converted to a PCB with one mouse click. The board designer can instantly renew the PCB from an updated version of schematic and keep existing placement, routed traces, board outline, mounting holes and other work. PCB and Schematic can be compared at any design stage to ensure they are identical. DipTrace has a powerful automatic router, superior to many routers included in other PCB layout packages. It can route a single layer and multilayer circuit boards, and there is an option to autoroute a single layer board with jumper wires, if required.<br /><br />DipTrace also provides you with external autorouter support. Smart manual routing tools allow users to finalize the design and to get the results they want in a blink of an eye. Accurate shape-based copper pour system with different possible fill types and thermals can be used to make planes or to reduce manufacturing costs. Other important features are Electrical Rule Check (ERC), Design Rule Check (DRC) and Net Connectivity Check – the functions that check connections in Schematic by different rules (pin type, short circuit, etc.), the clearance between layout objects, which ensures board accuracy, and connectivity of all nets not depending on how they are connected (with traces, thermals or shapes). DipTrace modules allow you to exchange schematics, layouts and libraries with other EDA and CAD packages. DipTrace Schematic Capture and PCB Layout also support popular netlist formats. Output formats are DXF, Gerber, Drill and G-code. Standard libraries include 50.000+ components.<br /></p><p><a target="_blank" href="http://www.diptrace.com/downloads/dipfree_en.exe">DipFree Download</a> here</p><p align="justify"> Try DipTrace and you will be surprised! DipTrace is a complete state-of-the-art PCB Design System. It includes: </p> <ul><li><p align="justify"><span class="gray"><b>PCB Layout</b></span> — PCB design with an easy to use manual routing tools, auto-router and auto-placer. </p></li><li><p align="justify"><span class="gray"><b>Schematic</b></span> — Schematic Capture and export to PCB or Spice. </p></li><li><p align="justify"><span class="gray"><b>Pattern Editor</b></span> — allows you to create part footprints. </p></li><li><p align="justify"><span class="gray"><b>Component Editor</b></span> — allows you to draw parts and make components. </p></li></ul><br /><table style="background-color: rgb(243, 243, 243); background-image: url(img/dot_lg.gif); width: 404px; height: 246px;" border="0" cellpadding="0" cellspacing="0"> <tbody><tr> <td width="8"><img src="http://diptrace.com/img/rc_tl.gif" alt="" border="0" height="8" width="8" /></td> <td style="text-align: center;" width="100%"><br /></td> <td width="8"><img src="http://diptrace.com/img/rc_tr.gif" alt="" border="0" height="8" width="8" /></td> </tr> <tr> <td colspan="3"> <table style="width: 322px; height: 35px;" align="center"> <tbody><tr><td align="center" width="50%"> <p><a href="http://diptrace.com/screenshots.php"><b>Watch DipTrace in action!</b></a></p> </td> <td align="center" width="50%"> <p><a href="http://diptrace.com/download.php"><b>Get 250-pin Freeware now!</b></a></p> </td></tr> </tbody></table> <table style="width: 379px; height: 163px;" border="0" cellpadding="0" cellspacing="6"> <tbody><tr> <td style="text-align: center;" width="50%"><a href="http://diptrace.com/screenshots.php"><img style="width: 187px; height: 142px;" src="http://diptrace.com/scr/scr2s.gif" alt="DipTrace screen example" border="0" /></a></td> <td align="center" width="50%"><a href="http://diptrace.com/screenshots.php"><img style="width: 198px; height: 150px;" src="http://diptrace.com/scr/scr1s.gif" alt="DipTrace screen example" border="0" /></a></td> </tr> <tr> <td align="center" valign="top"><p>Schematic Capture</p></td> <td align="center" valign="top"><p>PCB Layout</p></td> </tr> </tbody></table> </td> </tr> <tr> <td><img src="http://diptrace.com/img/rc_bl.gif" alt="" border="0" height="8" width="8" /></td> <td style="text-align: center;"><br /></td> <td><img src="http://diptrace.com/img/rc_br.gif" alt="" border="0" height="8" width="8" /></td> </tr> </tbody></table><br /><h2>DipTrace provides the following features:</h2> <p align="justify"> <span class="gray"><b>Easy to learn user interface</b></span><br />To design a schematic, simply select and place components onto your document and connect them together using the wire and bus tools. Multisheet design is supported. Then select the menu option 'Convert to PCB' to convert the schematic to PCB. Layout can be updated from Schematic in a few clicks at anytime. When you create or edit design objects they are highlighted to improve your work. <a href="http://diptrace.com/help/">Step-by-step tutorial</a> available from web-site guides you through the design process and allows to get started with ease. </p> <p align="justify"> <span class="gray"><b>Smart placement and auto-placement features</b></span><br />After converting Schematic to PCB layout, place board outline and arrange components. Then use "placement by list" for chips/connectors and auto-placement for other components to get acceptable result in a few minutes and start routing. </p> <p align="justify"> <span class="gray"><b>Easy to use manual and powerful automatic routing</b></span><br />DipTrace PCB software includes an advanced grid-based automatic router that is able to route single-layer and multi-layer boards. It is available with a 'rip-up and retry' algorithm. With Specctra DSN/SES interface you can use external shape-based or topological autorouter. Intelligent manual routing tools allow you to create and edit traces by 90, 45 degree or without any limitations. Curved traces are supported. Through, blind or buried vias can be used in automatic and manual routing. Board size is not limited. </p> <p align="justify"> <span class="gray"><b>Shape-based copper pour</b></span><br />Powerful copper pour system can help to reduce your manufacturing costs by minimizing the amount of etching solution required. To use it, all you have to do is insert a copper area on your board in the PCB Layout program and any pad or trace inside the selected area will be automatically surrounded with a gap of the desired size. Using copper pour you can also create planes and connect them to pads and vias (different thermal types are supported). </p> <p align="justify"> <span class="gray"><b>Advanced Verification Features</b></span><br />Schematic and PCB design modules have number of verification features that help control project accuracy on different design stages: The ERC function shows possible errors in Schematic pin connections using defined rules and allows you to correct errors step-by-step. DRC function checks the clearance between design objects, minimum size of traces, and drills. Errors are displayed graphically and you can fix them step-by-step and rerun the DRC in one click after any corrections. Net Connectivity Check verifies if all nets of PCB are electrically connected. This feature uses traces, copper pour filled area and shapes to control connectivity, then reports broken and merged nets with area details. Comparing to Schematic allows you to check if routed PCB is identical with Schematic. </p> <p align="justify"> <span class="gray"><b>Spice Support</b></span><br />Using DipTrace Schematic or Component Editor specify spice settings or attach models to the components. Then export .cir net-list of your Schematic to LT Spice or another simulation software to verify how it works. </p> <p align="justify"> <span class="gray"><b>Import/Export Features</b></span><br />Package modules allow you to exchange schematics, layouts and libraries with other EDA and CAD packages. DipTrace Schematic Capture and PCB Layout also support Accel, Allegro, Mentor, PADS, P-CAD, Protel and Tango netlist formats. </p><p> </p><p align="justify"> <span class="gray"><b>Manufacturing output formats</b></span><br />DipTrace provides support for a number of different manufacturing output formats. Using this PCB software you can produce N/C Drill files for numerically controlled (N.C.) drilling machines and RS-274X Gerber files for sending to board manufacturers. Vectorizing function allows to export true-type fonts and raster images. Also DipTrace supports DXF output. </p> <p align="justify"> <span class="gray"><b>Producing PCBs using milling method</b></span><br />DipTrace allows you to export edge polylines to DXF. The DXF files can be converted to G-code with <a href="http://www.dakeng.com/ace.html" target="_blank">Ace Converter</a> (it's free). Before edge exporting the DRC function of pcb layout program checks the design and shows possible problems if exist. </p> <p align="justify"> <span class="gray"><b>Standard component libraries</b></span><br />DipTrace package includes component and pattern libraries which contain 90,000+ components from different manufacturers. </p> <p align="justify"> <span class="gray"><b>Creation of your own libraries</b></span><br />Component and Pattern Editors allow to design your own symbols and patterns. To create complete components simply connect them together using Component Editor. </p> <p align="justify"> <span class="gray"><b>... and much more!</b></span> </p><p><br /></p>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com4tag:blogger.com,1999:blog-2756812074621187452.post-47529967363938654082009-11-10T10:15:00.000-08:002009-12-01T10:28:44.724-08:00Mentor Graphics: User2User India (U2U) - 04 December 2009, Bangalore<table style="text-align: left; margin-left: auto; margin-right: auto;" border="0" cellspacing="0" width="400"><tbody><tr><td colspan="2"><a title="http://user2user.mentor.com/bangalore-india" href="http://user2user.mentor.com/bangalore-india" target="_blank"><span title="http://user2user.mentor.com/bangalore-india" style="font-family:Arial;"><img style="width: 438px; height: 73px;" title="http://user2user.mentor.com/bangalore-india" alt="User2User" src="http://images.mentor.com/email/u2u_2009_bangalorens.jpg" border="0" /></span></a><br /><br /></td></tr> <tr> <td style="border-right: 1px solid rgb(234, 234, 234);" align="left" valign="top" width="400"> <table style="width: 401px; height: 557px;" border="0" cellpadding="2" cellspacing="0"> <tbody> <tr> <td style="padding: 2px 10px; background: rgb(181, 36, 66) none repeat scroll 0% 0%; -moz-background-clip: border; -moz-background-origin: padding; -moz-background-inline-policy: continuous;"> <h2 style="margin: 0pt; padding: 0pt; font-weight: normal; font-size: 11px; color: rgb(255, 255, 255); font-family: Arial,Helvetica,sans-serif;">USER2USER 2009</h2></td></tr> <tr> <td style="padding: 10px;"><br /><span style="font-family:Arial;"><span style="color: rgb(181, 36, 66);font-size:85%;" ><strong>User2User India 2009<br />December 4<br />Taj Residency, Bangalore</strong></span><br /><br /></span><span style="color: rgb(102, 102, 102);font-size:85%;" ><span style="font-family:Arial;">You are invited to </span><a title="http://user2user.mentor.com/bangalore-india" href="http://user2user.mentor.com/bangalore-india" target="_blank"><span title="http://user2user.mentor.com/bangalore-india" style="font-family:Arial;">User2User India 2009</span></a><span style="font-family:Arial;">, the Mentor Graphics user conference to be held on Friday, December 4 in Bangalore, India.<br /><br />Join us for a full day of technical sessions and gain immediately-useful knowledge in areas including System Design, Functional Verification & Emulation, Design 2 Silicon, Silicon Test and CFD.<br /><br /><strong>Keynote Speakers</strong> </span> </span><ul><span style="color: rgb(102, 102, 102);font-size:85%;" ><li><span style="font-family:Arial;">Wesley Ryder, Worldwide Technical Director, Mentor Graphics </span> </li><li><span style="font-family:Arial;">Vamsi Boppana, Xilinx Inc </span> </li><li><span style="font-family:Arial;">Pravin Desale, LSI Technologies (India) Pvt Ltd </span></li></span></ul><span style="color: rgb(102, 102, 102);font-size:85%;" ><span style="font-family:Arial;"><strong>Event Highlights</strong> </span> </span><ul><span style="color: rgb(102, 102, 102);font-size:85%;" ><li><span style="font-family:Arial;">User will present case studies and best practices on how they address their most pressing design challenges </span> </li><li><span style="font-family:Arial;">Get great insights on new techniques and methodologies used for leading challenges </span> </li><li><span style="font-family:Arial;">Learn the latest advancements and usage experience from users </span> </li><li><span style="font-family:Arial;">Great opportunity to meet other professionals like yourself and exchange expertise, tips and tricks, or industry happenings </span> </li><li><span style="font-family:Arial;">Enjoy great food and win prizes while you network with fellow EE designers </span></li></span></ul><span style="color: rgb(102, 102, 102);font-size:85%;" ><span style="font-family:Arial;">Registration ends on 30 November, 2009.<br /><br /></span> <table bgcolor="#b52442" border="0" cellpadding="2" cellspacing="0"> <tbody> <tr> <td align="middle" bgcolor="#b52442" valign="center"> <table bgcolor="#ffffff" border="0" cellpadding="5" cellspacing="1"> <tbody> <tr> <td align="middle" bgcolor="#b52442" valign="center" width="100%"><a title="http://user2user.mentor.com/bangalore-india" href="http://user2user.mentor.com/bangalore-india" target="_blank"><span title="http://user2user.mentor.com/bangalore-india" style="text-decoration: none; color: rgb(255, 255, 255);font-family:Arial;font-size:78%;" >LEARN MORE</span></a><span style="font-family:Arial;"> </span></td></tr></tbody></table></td></tr></tbody></table><br /></span> </td></tr></tbody></table></td></tr></tbody></table><div style="text-align: center;"> </div> <table style="width: 649px; height: 41px; text-align: left; margin-left: auto; margin-right: auto;" border="0" cellpadding="0" cellspacing="15"> <tbody> <tr> <td width="5"><span style="font-family:Arial;"> </span><br /></td></tr></tbody></table><div style="text-align: center;"><br /></div><table style="width: 649px; height: 41px; text-align: left; margin-left: auto; margin-right: auto;" border="0" cellpadding="0" cellspacing="15"><tbody><tr></tr></tbody></table><div> </div><span style="font-size:85%;"><input type="hidden"><input type="hidden"><span style="font-family:Arial;"> </span></span><div style="text-align: center;"> </div><div> </div> <div style="text-align: center;"><span style=";font-family:Arial;font-size:85%;" ><strong>REGISTER TODAY >>></strong></span></div> <div align="left"><div style="text-align: center;"><a title="http://user2user.mentor.com/bangalore-india" href="http://user2user.mentor.com/bangalore-india" target="_blank"><img title="http://user2user.mentor.com/bangalore-india" alt="User2User 2009 in Bangalore" src="http://images.mentor.com/email/u2u2009sig.gif" border="0" height="143" width="332" /></a></div> </div>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com2tag:blogger.com,1999:blog-2756812074621187452.post-23915671301491292822009-09-08T23:30:00.001-07:002009-09-08T23:33:59.245-07:00Apache Design Solutions Acquires Sequence Design<span style="font-size:130%;"><span style="font-weight: bold;">Apache Design Solutions Acquires Sequence Design</span></span> <p><em>Acquisition Expands Company’s Technology Leadership in Power and Noise Solutions to RTL Designs</em></p> <p>San Jose, California – September 8, 2009 – Apache Design Solutions, the technology leader in power and noise integrity for Chip-Package-Systems (CPS) convergence, today announced it has acquired the assets, including intellectual property, and foreign subsidiaries of Sequence Design, the EDA leader in RTL Design for Power (DFP)™ solution. Sequence operations will be integrated under Apache’s global research and development, sales, support and marketing functions. Vic Kulkarni, President and CEO of Sequence Design, will assume the role of Senior Vice President and General Manager of RTL Business Unit in Apache. Terms of the transaction were not disclosed.</p> <p>Through this acquisition, Apache expands power and noise product offerings from SoC, analog/mixed-signal, and package/PCB designs to the RTL where greater opportunity for power optimizations can be realized. The combination of Sequence’s technology and Apache’s power sign-off platforms raises the power-based solutions to the same level of importance as area and timing based tools.</p> <p>“Sequence Design has established a solid reputation and customer base in RTL power analysis and reduction,” said Andrew Yang, CEO of Apache, “This acquisition reinforces Apache’s business and product strategy for complete offering of advanced power and noise integrity solutions for chip-package-system convergence.”</p> <p>“Apache has demonstrated an impressive growth in the marketplace and established a critical mass of customer base, financial strength, and management experience. Our team looks forward to contributing to its continued success,” said Vic Kulkarni, President and CEO of Sequence.</p> <p>Sequence Products:</p><p>PowerTheater, PowerArtist, Cool Products and Columbus will continue to be supported by Apache.</p> <p><em>Apache Design SolutionsCPM, NSPICE, RedHawk, PakSI-E, PsiWinder, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc</em></p>Source:<br /><a href="http://www.apache-da.com/apache-da/Home/NewsandEvents/PressReleases/09.08.09.html">http://www.apache-da.com/apache-da/Home/NewsandEvents/PressReleases/09.08.09.html</a><span style="font-style: italic;"><br /></span><a href="http://www.reuters.com/article/pressRelease/idUS225568+08-Sep-2009+BW20090908">http://www.reuters.com/article/pressRelease/idUS225568+08-Sep-2009+BW20090908</a><span style="font-style: italic;"><br /></span><a href="http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=219700024">http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=219700024</a><span style="font-style: italic;"><br /></span>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-21386248135548144322009-07-23T04:39:00.000-07:002009-07-23T05:20:47.492-07:00IEEE 1801: UPF achieves formal standardisation as IEEE-1801<span style="font-weight: bold;">The </span><a style="font-weight: bold;" href="http://www.ieee.org/" target="_blank">IEEE</a><span style="font-weight: bold;"> and the EDA-industry alliance </span><a style="font-weight: bold;" href="http://www.accellera.org/" target="_blank">Accellera</a><br />Shrenik Mehta, chairman of Accellera observes, "Industry acceptance of the IEEE 1801 standard power format can help optimize the energy consumption of future electronic systems by enabling engineers and tools to characterize and improve semiconductor power usage much earlier in the design cycle." announced today that the IEEE has approved a new standard, IEEE 1801, "Standard for Design and Verification of Low Power Integrated Circuits." The standard is also known as Unified Power Format (UPF) 2.0, and engineers in many chip-design teams worldwide already employ it to convey aspects of an IC design that are critical to low-power specifications from one tool to another throughout an electronic system design, analysis, verification and implementation flow.<br /><p><a href="http://edablog.com/2009/03/19/accellera-upf-1801/"><span style="font-weight: bold;">EDA Blog</span></a>: The IEEE has approved a new IEEE 1801 standard for Design and Verification of Low Power Integrated Circuits. The standard is also known as Unified Power Format (UPF) 2.0. UPF (first developed by Accellera) and is currently supported by multiple vendors and is in use worldwide. This is the first time that UPF has undergone an IEEE standardization effort. The IEEE 1801 standard provides portability of low-power design specifications that can be used with a variety of commercial products throughout an electronic system design, analysis, verification and implementation flow. Enhancements to UPF in the new standard include support for bias supplies (N-well, P-well, Deep-N-Well, and Deep-P-Well), greater flexibility and capabilities in specification of power states, and enhanced semantic capabilities for merged power domains.</p><span style="font-weight: bold;">References</span>:<br /><a href="http://standards.ieee.org/">IEEE Standards Association</a><br /><a href="http://www.accellera.org/activities/p1801_upf/">http://www.accellera.org/activities/p1801_upf/</a><br /><a href="http://www.accellera.org/join/roster/">http://www.accellera.org/join/roster/</a><br /><a href="http://standards.ieee.org/announcements/pr_ieee1801.html">http://standards.ieee.org/announcements/pr_ieee1801.html</a><br /><br /><span style="font-weight: bold;">EDA supporting UPF</span>:<br /><ul><li class="noimg"><a href="http://www.magma-da.com/">Magma Design Automation</a></li><li class="noimg"><a href="http://www.mentor.com/">Mentor Graphics</a></li><li class="noimg"><a href="http://www.synopsys.com/">Synopsys Inc.</a></li></ul>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-6881743327483131502009-07-10T02:53:00.000-07:002009-07-10T02:55:23.407-07:00Application engineers (EDN Blog)<h3 class="blogPostTitle">Application engineers</h3><p>Application engineers are the unsung heroes of EDA. They have to blend the technical skills of designers with the interpersonal skills of salespeople. Most AEs start out as design engineers (or software engineers for the embedded market). But not all design engineers make it as AEs, partially because, as I’m sure you’ve noticed, not all design engineers have good interpersonal skills! There’s also another problem, memorably described to me years ago by Devadas Varma: “they’ve only been in the restaurant before; now they’re in the kitchen they’re not so keen on what it takes to prepare the food.” Being an AE means cutting more corners than being a design engineer, and some people just don’t have that temperament. An AE usually has to produce a 95% solution quickly; a design engineer has to take whatever time it takes to produce a 100% solution.</p> <p>AEs have a lot of options in their career path. As they become more senior and more experienced they have four main routes that they can take.<br /></p><p><a href="http://www.edn.com/blog/920000692/post/1110046111.html">Read More</a> - <a href="http://www.edn.com/blog/920000692/post/1110046111.html">http://www.edn.com/blog/920000692/post/1110046111.html</a></p><p><span style="font-weight: bold;">Source: </span><a href="http://www.edn.com/blog/920000692/post/1110046111.html"><span style="font-weight: bold;">EDN</span><br /></a></p>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-73418835299227458002009-07-10T02:44:00.000-07:002009-07-10T02:52:20.262-07:00Oasys Design Systems- RealTime Designer - Multi-Million Gate RTL Synthesis<a href="http://www.oasys-ds.com/index.html"><img src="http://www.oasys-ds.com/images/contact_01.gif" width="315" border="0" height="102" /></a><br /><span style="font-weight: bold;">Introducing RealTime Designer</span> (Connecting RTL to Silicon)<br />(<a href="http://www.oasys-ds.com/">Oasys Design Systems</a>)<br /><br />Oasys was founded in 2004 by a team of leading EDA developers, funded by successful entrepreneurs from the IC design and EDA business, with the intent of creating a new platform for IC implementation to address the 65 nanometer and below technology.<br /><br /> RealTime Designer operates at the RTL level and delivers stunning quality of results while doing it at speeds previously thought impossible and with a capacity of 100 million gates<br /><br /> Simply stated, RealTime Designer is a full chip, physical RTL synthesis product that provides a new platform for nanometer design delivering the following capabilities:<br /> <ul><li>20X - 60x run time advantage over existing tools</li><li>Best quality of results</li><li>Chip scale capacity</li><li>Plug and play with existing EDA flows</li><li>Day one usability</li><li>Dramatic reductions in P&R run times</li><li>The best starting point for physical implementation</li></ul><a href="http://edablog.com/2009/07/07/design-systems-synthesizes/"><span style="font-weight: bold;">EDA Blog</span></a>: (Source: Ken Cheung)<p>RealTime Designer follows a “Place First” methodology that takes the RTL, partitions it into blocks, places the RTL in the context of a floorplan and implements each block all the way to placement. Chip-level constraints are automatically propagated across the blocks and the design is optimized for the best possible quality of results. During the optimization phase, RealTime Designer will repartition the design at the RTL and re-implement until the chip-level constraints are met.</p> <p>Design teams must manually check for many results, such as design congestion, and send the design repeatedly through synthesis and layout. RealTime Designer is the first product to automate that process. Designers can give RealTime Designer the chip floorplan as input or, if no floorplan exists then Oasys will create a floorplan including macro, pin and I/O placement. At completion RealTime Designer produces a placed design and a netlist that meets the constraints in the context of the desired floorplan.</p> <p>Synthesizing a physical block using TSMC 65nm – 700k instances, 70 Macros, running at 600MHz, and a “golden” floorplan – RealTime Designer completed the task in just 20 minutes and achieving design closure after a single iteration in place and route. In the traditional approach on the same design, a single iteration of synthesis took 14 hours. Furthermore, it took 6 months of iterations to achieve the best result of -300ps Worst Negative Slack, and in the end was not able to achieve design closure.</p> <p>Real Time Designer takes in standard inputs, including Verilog, standard timing and physical libraries, SDC timing constraints, and floorplan. VHDL will be available later this year. Output has been tested through all the popular place and route systems.</p><p></p><span style="font-weight: bold;">Competitors</span>:<br /><a href="http://www.synopsys.com/">Synopsys</a> | <a href="http://www.cadence.com/">Cadence</a> | <a href="http://www.magma-da.com/">Magma</a><br /><br /><span style="font-weight: bold;">Related Info</span>:<br /><table border="0" cellpadding="0" cellspacing="0"><tbody><tr><td id="navbar" style="padding-left: 10px;" align="center"><a href="http://www.oasys-ds.com/index.html">home</a></td> <td id="navbar" style="padding-left: 10px;" align="center">|</td> <td id="navbar" style="padding-left: 10px;" align="center"><a href="http://www.oasys-ds.com/aboutus.html">about us</a></td> <td id="navbar" style="padding-left: 10px;" align="center">|</td> <td id="navbar_active" style="padding-left: 10px;" align="center"><a href="http://www.oasys-ds.com/products.html">products</a></td> <td id="navbar" style="padding-left: 10px;" align="center">|</td> <td id="navbar" style="padding-left: 10px;" align="center"><a href="http://www.oasys-ds.com/news.html">news</a></td> <td id="navbar" style="padding-left: 10px;" align="center">|</td> <td id="navbar" style="padding-left: 10px;" align="center"><a href="http://www.oasys-ds.com/careers.html">careers</a></td> <td id="navbar" style="padding-left: 10px;" align="center">|</td> <td id="navbar" style="padding-left: 10px;" align="center"><a href="http://www.oasys-ds.com/contact.html">contact us</a></td></tr></tbody></table>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-1855438390437342092009-06-26T01:00:00.000-07:002009-06-26T01:07:31.446-07:00VLSI Conference - Call for papers - January 3-7, 2010<table style="text-align: left; margin-left: auto; margin-right: auto;" width="780" border="0" cellpadding="0" cellspacing="0"><tbody><tr><td valign="top" width="390" align="left"><img src="http://www.vlsiconference.com/vlsi2010/images/top-1vlsi.gif" alt="VLSI Design 2010" title="VLSI Design 2010" width="390" height="99" /></td> <td valign="top" align="left"><img src="http://www.vlsiconference.com/vlsi2010/images/top-2embedded.gif" alt="VLSI Design 2010" title="VLSI Design 2010" width="390" height="99" /></td> </tr> <tr> <td valign="top" align="left"><img src="http://www.vlsiconference.com/vlsi2010/images/4th-title.gif" alt="VLSI Design 2010" title="VLSI Design 2010" width="390" height="31" /></td> <td valign="top" align="left"><img src="http://www.vlsiconference.com/vlsi2010/images/4th-title1.gif" alt="VLSI Design 2010" title="VLSI Design 2010" width="390" height="31" /></td></tr></tbody></table><br /><div style="text-align: center;"><img src="http://www.vlsiconference.com/vlsi2010/images/theme-VLSI.gif" alt="THEME: Affordable Technology for Emerging Markets" title="THEME: Affordable Technology for Emerging Markets" width="416" height="58" /> </div><p style="text-align: center;">This joint conference is a forum for researchers and designers to present and discuss various aspects of VLSI design, electronic design automation (EDA), enabling technologies, and embedded systems. It covers the entire spectrum of activities in the two vital areas of very large scale integration (VLSI) and embedded systems, which underpin the semiconductor industry. The five-day technical program will consist of three days of regular paper sessions, special sessions, embedded tutorials, industry presentation sessions, panel discussions, design contests and industrial exhibits, and two days of full-day tutorials.</p><div style="text-align: center;"> Electronic systems are ubiquitous today in multiple applications, with emerging markets in health-care, entertainment and machine intelligence spurring several new ones. These markets often hinge delicately on the right blend of technology and affordability. Accordingly, the theme for this conference is set as “Affordable Technology for Emerging Markets”.<br /><br /><a href="http://www.vlsiconference.com/vlsi2010/onlinesubmission.htm">Submit Online</a> - <a href="http://www.vlsiconference.com/vlsi2010/onlinesubmission.htm">http://www.vlsiconference.com/vlsi2010/onlinesubmission.htm</a><br /><br /></div><p style="text-align: center;"><strong class="subHead1">Submission site now open:</strong><br /> Please make all submissions at <a href="https://cmt.research.microsoft.com/VLSI2010/" class="link_menu_blue1">https://cmt.research.microsoft.com/VLSI2010/</a></p><div style="text-align: center;"> There are individual tracks for submission </div><ul style="text-align: center;" class="list2"><li>Papers (includes regular papers, proposals for special sessions, panels, embedded tutorials)</li><li>Full-day and Hands-on Tutorials </li><li>Design-EDA-Systems Contest</li></ul><div style="text-align: center;"> </div><p style="text-align: center;"><strong class="subHead">IMPORTANT:</strong> Last date for all submissions is <span class="subHead1">July 10, 2009</span><br /> <br /> </p><div style="text-align: center;"> </div><p style="text-align: center;" class="subHead"><strong>Submission Guidelines</strong> </p><div style="text-align: center;"> </div><p style="text-align: center;">Submission guidelines for tutorials are now available at<br /> <a href="http://www.vlsiconference.com/vlsi2010/call_callfortutorials.html" class="link_menu_blue1">http://www.vlsiconference.com/vlsi2010/call_callfortutorials.html</a> </p><div style="text-align: center;"> </div><p style="text-align: center;">Submission guidelines for papers are available at<br /> <a href="http://www.vlsiconference.com/vlsi2010/call_callforpapers.htm" class="link_menu_blue1">http://www.vlsiconference.com/vlsi2010/call_callforpapers.htm</a></p><table style="text-align: left; margin-left: auto; margin-right: auto;" width="440" border="0" cellpadding="0" cellspacing="0"><tbody><tr><td valign="top" width="440" align="center"><br /></td></tr><tr><td valign="middle" align="center"><br /></td></tr><tr><td valign="top" align="left"><table class="frame1" width="440" border="0" cellpadding="0" cellspacing="0"><tbody><tr><td valign="middle" width="553" align="center" height="180"><table width="440" border="0" cellpadding="4" cellspacing="1"><tbody><tr valign="middle" align="center"><td colspan="3" style="background: transparent url(images/call-forpaper-bg.gif) repeat-x scroll 0% 0%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;" class="form6" height="30"><b>IMPORTANT DATES</b></td> </tr> <tr valign="middle"> <td colspan="3" class="form5" align="left" height="20">Submissions:</td> </tr> <tr valign="middle"> <td class="form22" width="303" align="left" height="20">Regular Papers</td> <td class="form22" width="4" align="left" height="20">:</td> <td class="form5" width="154" align="left" height="20">July 10, 2009 </td> </tr> <tr valign="middle"> <td class="form22" align="left" height="20">Special sessions</td> <td class="form22" align="left" height="20">:</td> <td class="form5" align="left" height="20">July 10, 2009 </td> </tr> <tr valign="middle"> <td class="form22" align="left" height="20">Full-day tutorials</td> <td class="form22" align="left" height="20">:</td> <td class="form5" align="left" height="20">July 10, 2009 </td> </tr> <tr valign="middle"> <td class="form22" align="left" height="20">Embedded tutorials</td> <td class="form22" align="left" height="20">:</td> <td class="form5" align="left" height="20">July 10, 2009 </td> </tr> <tr valign="middle"> <td class="form22" align="left" height="20">Panel proposals</td> <td class="form22" align="left" height="20">:</td> <td class="form5" align="left" height="20">July 10, 2009 </td> </tr> <tr valign="middle"> <td class="form22" align="left" height="20">Acceptance notification </td> <td class="form22" align="left" height="20">:</td> <td class="form5" align="left" height="20">September 15, 2009</td> </tr> <tr valign="middle"> <td class="form22" align="left" height="20">Fellowship application due </td> <td class="form22" align="left" height="20">:</td> <td class="form5" align="left" height="20">October 1, 2009</td></tr></tbody></table></td></tr></tbody></table></td></tr></tbody></table><br /><span style="font-weight: bold;">Source</span>: VLSIConferenceAnenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-79939367991700923992009-05-08T02:33:00.000-07:002009-05-08T02:41:49.118-07:00Runtime Design Automation - FlowTracer<p><a href="http://www.rtda.com/"><span >Runtime Design Automation</span></a><span > was founded in May, 1995 in Alameda, CA. Runtime Design Automation's main offices are now located in Santa Clara, CA. The company is privately held and privately funded.<br />The innovative technology behind our <strong>Flowtracer</strong> design flow manager comprises run-time tracing for design management. This technology was initially developed at the University of California at Berkeley between 1989 and 1991; it was extended and tested at Siemens from 1992 to 1995.<br />Runtime Design Automation was issued U.S. Patent 5,634,056 in May, 1997 on intelligent change propagation.<br />In December 2000 Runtime Design Automation opened a Research and Development office in Padova, Italy. The Italian group was reabsorbed by the California team in 2005.<br /><strong>Products Overview</strong>:</span></p><p><a href="http://www.rtda.com/products/licensemonitor.html"><span >LicenseMonitor</span></a><span ><br />License Monitoring. This is our subsystem to monitor licenses (including FLEXlm) and all other design resources, such as machines, file systems, processes.<br /></span><a href="http://www.rtda.com/products/networkcomputer.html"><span >NetworkComputer</span></a><span ><br />Network Computing. This is our batch processing system, based on the FlowTracer technology It is targeted for the efficient utilization of hardware and software computing resources at the corporate level. NetworkComputer also allows static definitions of flows.<br /></span><a href="http://www.rtda.com/products/flowtracer.html"><span >FlowTracer</span></a><span ><br />Workflow Management. This is the solution for total management of complex workflows. A unique technology, called Runtime Tracing™ guarantees the correctness of the flow representation and its efficient execution (see our </span><a href="http://www.rtda.com/download/paper2002.pdf"><span >white paper</span></a><span > for info). A patented technique known as Runtime Change Propagation Control allows FlowTracer to move beyond file timestamps and use, for example, MD5 signatures to determine changes to files. </span></p><p><span ><img src="http://www.rtda.com/images/products/dependency-graph.gif" /><br /><br /><em>All software is supported on AIX, HPUX, MAC OS-X, Linux, Solaris, Windows (NT,2000,XP)</em>. </span></p>VLSICore - Technology Expertshttp://www.blogger.com/profile/11189927779337620106noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-21543688609810360692009-05-01T11:46:00.000-07:002009-05-01T11:51:15.647-07:00EDA Utilities by Eng Han<img alt="http://www.eda-utilities.com/eda_utilities_logo.jpg" src="http://www.eda-utilities.com/eda_utilities_logo.jpg" /><br /><br /><span style="font-family:Arial,Helvetica,Chicago;color:NAVY;">A lot of EDA tools are used in the design and implementation of IC chip. While the EDA tools are powerful, there are always features that are not available to address some of the IC design and implementation needs. Some of these missing features can be easily developed in a short time while some may take a longer time. The latter forms the niche for EDA Utilities. </span><br /><span style="font-family:Arial BOLD,Helvetica BOLD,Chicago;color:NAVY;"><br /><a href="http://www.eda-utilities.com/book_kungfu.htm" target="content"><img src="http://www.eda-utilities.com/art_work/kungfu_cover.jpg" width="120" border="0" /><br />CMOS Transistor Layout KungFu</a><br /><br /><a href="http://www.eda-utilities.com/book_pnr.htm" target="content"><img src="http://www.eda-utilities.com/art_work/pnr_cover.jpg" width="120" border="0" /><br />Gate To GDSII</a><br /><br /><a href="http://www.eda-utilities.com/book_verilog.htm" target="content"><img src="http://www.eda-utilities.com/art_work/verilog_training_slide.jpg" border="0" /></a><br /><br /><span style="font-weight: bold;">EDA Tools from EDA-Utilities</span>:<br /></span><br /><br /><a href="http://www.eda-utilities.com/vo.htm" target="content"><img src="http://www.eda-utilities.com/art_work/vo.jpg" border="0" /></a><br /><br /><a href="http://www.eda-utilities.com/lv.htm" target="content"><img src="http://www.eda-utilities.com/art_work/lv.jpg" border="0" /></a><br /><br /><a href="http://www.eda-utilities.com/ls.htm" target="content"><img src="http://www.eda-utilities.com/art_work/ls.jpg" border="0" /></a><br /><br /><a href="http://www.eda-utilities.com/cv.htm" target="content"><img src="http://www.eda-utilities.com/art_work/cv.jpg" border="0" /></a><br /><br /><span style="font-weight: bold;">Source</span>: <a href="http://www.eda-utilities.com/">http://www.eda-utilities.com/</a>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com1tag:blogger.com,1999:blog-2756812074621187452.post-38578213592419612392009-03-30T10:10:00.000-07:002009-03-30T10:47:22.559-07:00VLSI Video Lectures from NPTEL (from IIT/IISc)<div id="watch-this-vid" class="watch-this-vid-longform"> <script type="text/javascript" src="http://www.google-analytics.com/ga.js"></script> <script type="text/javascript"> var pageTracker = _gat._getTracker("UA-5706458-1"); pageTracker._initData(); function urchinTracker (a) {pageTracker._trackPageview(a);} </script> <script type="text/javascript"> var page = "" + "/VideoWatch" + "/" + "Lecture - 1 Introduction on VLSI Design"; pageTracker._trackPageview(page);</script></div><div id="watch-other-vids"><div id="watch-channel-brand-cap"><div style="text-align: center;"><a href="http://www.youtube.com/user/nptelhrd" onmousedown="urchinTracker('/Events/VideoWatch/ChannelBrandBanner');"><img src="http://i3.ytimg.com/u/640y4UvDAlya_WOj5U4pfA/watch_header.jpg" border="0" /></a></div> </div></div><div style="text-align: center;"><span style="font-weight: bold;">VLSI Design - Video Lectures from NPTEL</span> (from IIT/IISc)<br /><span style="font-weight: bold;">National Programme on Technology Enhanced Learning</span> (NPTEL)<br /></div>For more details on NPTEL - visit <a href="http://nptel.iitm.ac.in/">http://nptel.iitm.ac.in</a><br /><a href="http://www.youtube.com/user/nptelhrd">http://www.youtube.com/user/nptelhrd</a> - YouTube Videos<br /><br /><table class="playlist" width="100%" border="0" cellpadding="2" cellspacing="0"><tbody><tr valign="top"><td><div style="margin-right: 10px;"><div class="vCluster120WideEntry"><div class="vCluster120WrapperOuter"><div class="vCluster120WrapperInner"><a id="video-url-Y8FvvzcocT4" href="http://www.youtube.com/view_play_list?p=D2350A83B752C861&playnext=1&playnext_from=PL" rel="nofollow"><img title="Electronics - Digital VLSI System Design" src="http://i2.ytimg.com/vi/Y8FvvzcocT4/default.jpg" class="vimgCluster120" alt="Electronics - Digital VLSI System Design" /></a><div class="video-corner-text"><span>55 videos</span></div></div></div></div></div></td> <td width="100%"> <div class="title"> <a href="http://www.youtube.com/view_play_list?p=D2350A83B752C861">Electronics - Digital VLSI System Design</a> <span dir="ltr" class="facets"> 55 Videos</span> </div> <div class="desc">Lectures by Prof S.Srinivasan,<br />Dept of Electrical Engineering,<br />IIT Madras</div> </td> <td valign="middle" align="right" nowrap="nowrap"> <div class="playlistLinks"> <a href="http://www.youtube.com/view_play_list?p=D2350A83B752C861&playnext=1&playnext_from=PL">Play All</a> <form name="subscribeToPlaylistD2350A83B752C861" method="post" action="/subscription_center"> <input name="session_token" value="Isyn_S7xe6plPkzk4B4hVqHKdup8MA==" type="hidden"> <input name="add_user_playlist" value="D2350A83B752C861" type="hidden"> <a href="javascript:%20document.subscribeToPlaylistD2350A83B752C861.submit()">Subscribe</a> </form> <a href="javascript:share('D2350A83B752C861');">Share</a> </div></td></tr></tbody></table><br /><br /><table class="playlist" width="100%" border="0" cellpadding="2" cellspacing="0"><tbody><tr valign="top"><td><div style="margin-right: 10px;"><div class="vCluster120WideEntry"><div class="vCluster120WrapperOuter"><div class="vCluster120WrapperInner"><a id="video-url-VaIMp-sZe0U" href="http://www.youtube.com/view_play_list?p=018645397D9487AF&playnext=1&playnext_from=PL" rel="nofollow"><img title="Electronics - VLSI Design" src="http://i3.ytimg.com/vi/VaIMp-sZe0U/default.jpg" class="vimgCluster120" alt="Electronics - VLSI Design" /></a><div class="video-corner-text"><span>40 videos</span></div></div></div></div></div></td> <td width="100%"> <div class="title"> <a href="http://www.youtube.com/view_play_list?p=018645397D9487AF">Electronics - VLSI Design</a> <span dir="ltr" class="facets"> 40 Videos</span> </div> <div class="desc">Lecture Series on VLSI Design by Dr.Nandita Dasgupta, Department of Electrical Engineering, IIT Madras.</div> </td> <td valign="middle" align="right" nowrap="nowrap"> <div class="playlistLinks"> <a href="http://www.youtube.com/view_play_list?p=018645397D9487AF&playnext=1&playnext_from=PL">Play All</a> <form name="subscribeToPlaylist018645397D9487AF" method="post" action="/subscription_center"> <input name="session_token" value="Isyn_S7xe6plPkzk4B4hVqHKdup8MA==" type="hidden"> <input name="add_user_playlist" value="018645397D9487AF" type="hidden"> <a href="javascript:%20document.subscribeToPlaylist018645397D9487AF.submit()">Subscribe</a> </form> <a href="javascript:share('018645397D9487AF');">Share</a> </div></td></tr></tbody></table><br /><br /><span style="font-weight: bold;">Source</span>: <a href="http://nptel.iitm.ac.in/">http://nptel.iitm.ac.in</a>Anenthttp://www.blogger.com/profile/05350187404828738197noreply@blogger.com0