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VLSICore deals with VLSI design on SoC / ASIC / FPGA design flows. It includes,

  • Digital Logic design, Full-Custom/Semi-Custom design.
  • Microprocessors, DSP, Telecom more.
  • Technology: 32nm, 20nm, 14nm and beyond.
  • Foundry: TSMC, GF, UMC, IBM, Tower
  • Standard / IO Cell library preparation, Intellectual Property [Memories, SRAMs, DRAMs, PCI, USB, Audio/Video CODEC], VDSM/UDSM.
  • Verilog, PLI, VHDL, EDIF, System Verilog, SystemC
  • Design Entry, Simulation, Formal Verification, Synthesis.
  • Floorplanning, HF Net Synthesis, Placement, Clock Tree Synthesis, Routing, Physical Verification, RC Extraction, DFM, OPC, Tape-Out.
  • Shell, Perl, Tcl, Python, Tk/Tix, Scheme, C/C++, API, ...
  • Analog design, SPICE, Simulation, RF, PLL, High Speed CMOS, MEMS, ...
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  • EDA: Synopsys, Cadence, Mentor, Magma, ATopTech, Oasys, Xilinx, Altera, Atmel, ...
  • Open Source EDA tools, Open Source : ASIC design and technology.

Friday, October 28, 2011

Mentor Graphics User2User Conference 2011 - Bangalore - 02 Dec 2011

Mentor Graphics User2User - INVITATION

User2User 2011 India

You are invited to User2User India 2011, the International Mentor Graphics user conference to be held on December 02, 2011 in Bangalore, India.
Join us for a full day of technical sessions and gain immediately-useful knowledge in areas including Functional Verification, Silicon Test, Design 2 Silicon and System Design. Meet technical experts from user group of Mentor Graphics, Mentor technical staff and see product demos, learn best practices from other Mentor customers, and network with your colleagues. It all happens on:

Date: December 02, 2011
Location: Vivanta by Taj on MG Road (formerly Taj Residency), Bangalore
41/3 Mahatma Gandi Road
Bangalore 560001

Don't miss out on this excellent networking and learning opportunity.

Register today!

Registration ends on 30 Nov, 2011
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