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VLSICore deals with VLSI design on SoC / ASIC / FPGA design flows. It includes,

  • Digital Logic design, Full-Custom/Semi-Custom design.
  • Microprocessors, DSP, Telecom more.
  • Technology: 32nm, 20nm, 14nm and beyond.
  • Foundry: TSMC, GF, UMC, IBM, Tower
  • Standard / IO Cell library preparation, Intellectual Property [Memories, SRAMs, DRAMs, PCI, USB, Audio/Video CODEC], VDSM/UDSM.
  • Verilog, PLI, VHDL, EDIF, System Verilog, SystemC
  • Design Entry, Simulation, Formal Verification, Synthesis.
  • Floorplanning, HF Net Synthesis, Placement, Clock Tree Synthesis, Routing, Physical Verification, RC Extraction, DFM, OPC, Tape-Out.
  • Shell, Perl, Tcl, Python, Tk/Tix, Scheme, C/C++, API, ...
  • Analog design, SPICE, Simulation, RF, PLL, High Speed CMOS, MEMS, ...
  • DFM (Design for Manufacturing)
  • EDA: Synopsys, Cadence, Mentor, Magma, ATopTech, Oasys, Xilinx, Altera, Atmel, ...
  • Open Source EDA tools, Open Source : ASIC design and technology.

Wednesday, July 28, 2010

EDA Tech Forum - 2010 - Bangalore & New Delhi (India)

EDA Tech Forum India

EDA TECH FORUM INDIA
Delivering the Latest in 10X Design Improvements

Two Locations:
Bangalore- Wednesday, August 18, 2010
New Deli - Friday, August 20, 2010
8:00 – 17:50

Join other EE designers and engineers at one of two complimentary EDA Tech Forums in India - Bangalore and New Delhi. This year's event series features a new lineup of speakers, sponsors, and technology tracks in a one-day event that provides an excellent mix of educational and networking opportunities.

Create your personal agenda with tracks in:

  • Maximizing Front-end Design: From ESL through RTL
  • Accelerate Time to Manufacturing
  • Increase Productivity in System-level Design
  • Innovations in Embedded Software and User Interface Development

Start the day with exciting keynote speakers, like Pamela Kumar of IBM, Manjunath Hebbar of HCL Technologies, and Pravin Madhani of Mentor Graphics as he discusses how in the next five years, 10X improvements in design methodologies are needed. After attending in-depth technical breakout sessions, there will also be plenty of time to meet with leading EDA solution providers in the multi-vendor fair.

Event Highlights:

  • Attend in-depth technical sessions from sponsors
  • Test drive new tools from EDA solution providers at the multi-vendor fair
  • Enjoy great food and win prizes while you network with fellow EE designers

Guarantee your participation at the EDA Tech Forum. Register today.

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Friday, July 23, 2010

Gary Smith EDA market statistics 2010: Summary

Gary Smith EDA market statistics 2010: Summary

(July 22, 2010) -- These market statistics were compiled by Nancy Wu & Mary Olsson, part of the Gary Smith EDA team. The biggest change in 2009 was Mentor passing Cadence to become number two in product sales in EDA. This is an indication of the market shift caused by the move into the ESL Methodology. Synopsys remains a strong number one.

Mentor also grabbed #2 overall in IC design. With the acquisition of Valor, Mentor is also now 3× as large as its next competitor in PCB design.

We believe that the recent changes in Cadence has stopped their market share decline, similar to the changes made at Mentor, bringing in Walden Rhines, during the switch to the RTL design methodology.

Read more to know the statistics report - Click Here

Source: This article is from Solid State Technology

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