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Thursday, February 12, 2009
Modern and future 45/32 nm and below technologies are bringing new challenges for EDA tools. Physical verification is one of design flow areas where complexity of new processes in layouts combines with huge amount of data. On other hand, semiconductor industry still uses DRC/LVS tools that are based on core algorithms and principles created in last century. It creates significant bottleneck in design process causing losses of time and money for semiconductor companies.
To address requirement of modern and future designs, POLYTEDA Software Corporation is developing next generation physical verification system based on new revolutionary approaches. New tool is using unique proprietary set of algorithms and principles. Among them are processing subset of rules for several layers in “one shot”, parallel and distributed processing based on unique hierarchical approach, dynamic optimization of DRC/LVS process “on fly” using elements of artificial intelligence, and many others.
Usage of new technology allows reach speed close to theoretical limits. Preliminary calculation shows that new tool will be able to process the biggest currently available designs under one hour time limit. Almost linear speed dependency and scalability in handling huge amount of data allows processing layouts 10-100 times bigger than the biggest designs currently available.
PowerDRC will cover all physical verification needs of semiconductor industry at least for next 10-20 years. It is a tool that is going to last practically forever.Source: http://www.polyteda.com/
ATopTech was founded in 2004 by a team of leading EDA physical design implementation experts expressly to build new technology, from scratch, to deal with these issues design at 90nm and below. Aprisa, the result of these efforts, shipped to customers in December 2006 and has been used successfully in several 65nm tapeouts throughout 2007. Aprisa is currently in active use in several 40nm design efforts.
Aprisa is a complete netlist-to-GDSII physical design solution, including floorplanning, placement, clock-tree synthesis and optimization, global and detailed routing, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV and MCMM analysis. In addition, Aprisa uses state-of-the-art multi-threading and distributed processing technology across the solution to further speed up the process and avoid the exploding runtime issues with modern nanoscale design.
- Channeled and channel-less floorplans, or a mix of both,
- Rectilinear floorplans,
- Multiple libraries, and multi-height standard cells.
- Parametric route for power/ground grid creation
- Complex floorplan / placement constraints including rectilinear regions, multi-height cells, and mixed/overlapping sites,
- Efficient High Fan-out Synthesis
- Leakage power optimization
- Area Recovery
- Cluster-based clock trees or meshes
- Gated and generated clocks
- Synchronization of generated clock pins
- Automatic clock gate cloning and de-cloning
- Matching of latency targets specified by user for any pins
- Automatic creation of special routing constraints (layer, double width/spacing/via, shielding, etc.)
- Low-Power Clock Tree Synthesis
- Very fast, typically 5 minutes per million instances
- Read SDC natively without any translation
- Tight correlation to Primetime-SI and CeltIC
- Native OCV timing analysis
- CRPR Support (clock reconvergence pessimism removal)
- Timing browser (see diagram)
- Multi-threaded engine with near linear performance. An 8 cpu machine will achieve 7-7.5X the performance of a single CPU. Routes 250K instance in about 5 minutes on an 8 CPU machine.
- Supports all 90/65/45nm design rules
- Supports special routing rules such as double wide, double spaced, shielding, double vias, etc.
- Support for DFM issues such as wire-spreading, double-vias, and complex design rules such as end-of-line spacing/extension, min edge, min enclosure, etc.
- All routing done in-route rather than post processing steps
- Can iterate with precision optimization and MCMM timing engine for optimal results.
ATopTech Closes Successful 2008, Reaches Revenue Milestone
- Digital IC Thermal Analysis
The FireBolt thermal simulator computes full-chip temperatures with resolution down to the device and interconnect levels, and integrates smoothly into standard digital IC design flows. The software is fast and scalable, with the capacity to handle very large designs.
The output is a full-chip, 3-D temperature map, which can be used to reveal hotspots and excessive temperature variations. The temperature data also can be used to add thermal awareness to power, timing and electromigration analysis tools.
To run FireBolt, you need to provide a thermal technology file (die stack-up) for the foundry process, and thermal information for the package. FireBolt obtains the design layout and the power source information from your design environment to create a full 3-D temperature analysis of the design. It outputs instance-specific temperatures, wire temperatures and device powers. This information can be annotated into simulation to determine the thermal impact on the circuit's performance and reliability.
FireBolt is intended for use at several points in the design flow, from floorplanning to final sign-off. In the early front-end stage it makes use of information at the block-level, such as the area estimates and power estimates. In the later, back-end stages, FireBolt has the capacity to complete the full analysis, even with many more metal shapes and large number of instances and their power dissipations.
FireBolt takes into account the influence of the package thermal characteristics on the die temperatures.
FireBolt runs in multiple modes that allow the user to trade off between speed and accuracy, and enables control on the levels of resolution.More...
Also see: CircuitFire
Source: Gradient Design Automation