Magma - Blast Fusion

Blast Fusion® is an advanced netlist-to-GDSII chip implementation system for high-performance, high-complexity and low power designs being implemented in 90-nm and finer process geometries. Blast Fusion delivers complete design closure with better timing, smaller area, lower power, better yield, faster turnaround time and higher capacity than conventional point-tool flows.

• Super-high capacity allows designs of up to 5 million gates to be implemented flat on a 32-bit Linux machine, or up to 6 million gates to be implemented flat on a 64-bit Linux machine.Faster runtime is achieved through unified engines and efficient algorithms. 2-milliongate designs can be completed overnight.
• Unmatched timing and area results are enabled through the FixedTiming® methodology, SuperCell™ abstraction, integrated clock tree technology, OCV analysis and optimization, and concurrent multi-mode and multi-corner analysis and optimization.
• Significant leakage and dynamic power reduction is achieved through an integrated implementation flow using multiple threshold voltage (multi-Vt) cells and multiple voltage support, without sacrificing performance.
• Proven 90-nm design support for major silicon vendors and foundries is provided through design rules and design-formanufacturability capabilities.

EDA Vendor: Magma Design Automation - http://www.magma-da.com/
Product Page: http://www.magma-da.com/products-solutions/digitaldesign/blastfusion.aspx
Support: https://molten.magma-da.com/
Tutorials: N/A
Useful Links: N/A
Also see: N/A
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Source: Magma Design Automation

Olympus-SoC (Place & Route System)

Olympus-SoC™ is a complete IC implementation (netlist-to-GDSII) solution targeted at 65nm/45nm designs, which augments Mentor Pinnacle™, the industry’s leading Design for Variability solution.

Olympus-SoC gives designers the ability to optimize designs subject to variations in design modes, as well as lithography and other manufacturing processes windows, in a comprehensive and holistic fashion. Advanced multi-corner, multi-mode, (MCMM) technology provides timing optimization across a large number of design and process corners throughout the design flow, ensuring fast design-for-manufacturing closure. Integral to Olympus-SOC is Mentor's next-generation detailed routing architecture that incorporates variation-aware timing optimization and litho-modeling to address OPC/RET effects early in the design cycle.

With its high capacity implementation architecture, Olympus-SoC provides these advanced capabilities even for the largest designs at 45nm and beyond.

EDA Vendor: Mentor Graphics - http://www.mentor.com/ (Sierra Design Automation)
Product Page: http://www.mentor.com/products/ic_nanometer_design/cl_floorplan/olympus/index.cfm
Support: http://supportnet.mentor.com/
Tutorials: N/A
Useful Links: N/A
Also see: Mentor Pinnacle™
Related News:
Sierra Design Automation Delivers Olympus-SoC Lithography-Driven IC-Implementation System for 65-nm and 45-nm Designs
http://www.soccentral.com/results.asp?CatID=552&EntryID=19653
Mentor's Olympus-SoC Place-and-Route System Slashes Design Closure Times with Parallel Timing Analysis and Optimization Technology
http://www.soccentral.com/results.asp?EntryID=27075

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Source: Mentor Graphics

PrimeTime (PT) - Static Timing Analysis

Overview
Timing closure in today's advanced designs remains the number one challenge for designers today, especially at 65-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure.

The PrimeTime STA Solution
The Synopsys PrimeTime® static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry's de-facto gold standard for gate-level static time analysis with the capacity and performance for 50+ million-instance chips being designed at 65-nm and below. The PrimeTime solution is a key component of the Galaxy Design Platform.

With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It delivers to designers extensive timing analysis checks, advanced analysis techniques, golden delay calculator, advanced modeling, unmatched productivity and ease of use, a graphical user interface, and industry-wide ASIC vendor sign-off and foundry support.

EDA Vendor: Synopsys - http://www.synopsys.com/
Product Page: http://www.synopsys.com/products/analysis/primetime_ds.html
Tutorials:
http://www.ece.virginia.edu/~mrs8n/cadence/SynthesisTutorials/PrimeTutorial2.pdf
http://www2.informatik.uni-jena.de/~doersing/lehre/ps/sn99.10_dok/static/print/pttut.pdf
Useful Links: N/A
Datasheet: http://www.synopsys.com/products/analysis/primetime_ds.pdf
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Source: Synopsys