http://parts.jpl.nasa.gov/asic/Glossary.html
List of VLSI Acronyms:
A/D: Analog to Digital
ASIC: Application Specific Integrated Circuit
ATPG: automatic test pattern generation
BILBO: built-in logic block observation
BIST: built-in self-test
CAD: computer-aided design
CAE: computer-aided engineering
CAT: computer-aided testing
CDR: critical design review
CE: concurrent engineering
CLB: Configurable Logic Block
CMOS: Complimentary Metal Oxide Semi-conductor
CPLD: Complex Programmable Logic Device
CPU: central processing unit
CSA: Carry Save Adder
CSD: Canonical Signed Digits
CZT: Chirp-z Transform
DCM: Digital clock Manager
DESC: Defense Electronics Supply Center
DFT: design for test
DFT: Discrete Fourier Transform
DRC: design rule check
DSP: Digital Signal Processing
ECL: emitter-coupled logic
EDA: electronic design automation industry
EDAC: error detection and correction
EDIF: electronic design interchange format
EEPROM: Electrically Erasable Programmable Read Only Memory
EPROM: Electrically Programmable Read Only Memory
ERC: electronic design augomation
FDL: fault detection and localization
FFT: Fast Fourier Transform
FIR: Finite Impulse Response
FPGA: Field Programmable Gate Arrays
FPLD: Field programmable Logic Devices.
GA: gate array
GaAs: gallium-arsenide
HDL: hardware description language
HOL: high-order logic
I/O input/output
IEEE Institute of Electrical and Electronics Engineers
IIR: Infinite Impulse Response
ISE: Integrated Synthesis Environment
JAN Joint-Army-Navy
JEDEC Joint Electron Device Engineering Council
JTAG Joint Test Action Group
LAB: Logic Array Blocks
LC: Logic Cell
LCC leadless chip carrier
LE: Logic Element
LET linear energy transfer
LFSR linear feedback shift register
LSB: Least Significant Bit
LSSD level-sensitive scan design
LTI: Linear Time Invariant
LTPD lot tolerance percent defective
LUT: Look-Up Table
MAC: Multiply Accumulate
MAG: Multiplier Adder Graph
MAX: Multiple Array Matrix
MSB: Most Significant Bit
NRE nonrecurring engineering (charges)
PAL: Programmable Array Logic
PDA percent defective allowable
PDR preliminary design review
PG pattern-generation (tape)
PGA pin grid array
PIA: Programmable Interconnect Array
PLA: Programmable Logic Array
PLL: Phase Locked Loop
PM parametric monitor
QCI quality conformance inspection
QCRIT critical charge
QML Qualified Manufacturers List
QMP Quality Management Plan
QPL Qualified Products List
RAG: Reduced Order Graph
RAM: Random Access Memory
ROM: Read Only Memory
RTL register-transfer level
SC standard cell
SD: Signed Digit
SEC standard evaluation circuit
SEE single-event effect
SEL single-event latchup
SEU single-event upset
SMD standardized military drawing
SOC: System On Chip
SOI silicon-on-insulator
SOS silicon-on-sapphire
SOW statement of work
SPC statistical process control
SPICE simulation program with IC emphasis
SRAM: Synchronous Random Access Memory
SRL shift register latch
TAP test access port
TCI technology conformance inspection
TCV technology characterization vehicle
TDDB time-dependent dielectric breakdown
TID total ionizing dose
TMT triple modular redundancy
TQM total quality management
TRB technology review board
TRSL test requirements and specification language
TTL transistor-transistor logic
VHDL: VHSIC Hardware Descriptive Language
VHSIC: Very High Speed Integrated Circuit
VLSI: Very Large Scale Integrated Circuit
WAVES waveform and vector exchange program
Courtesy/Source: NASA
