Apache Design Solutions Acquires Sequence Design

Apache Design Solutions Acquires Sequence Design

Acquisition Expands Company’s Technology Leadership in Power and Noise Solutions to RTL Designs

San Jose, California – September 8, 2009 – Apache Design Solutions, the technology leader in power and noise integrity for Chip-Package-Systems (CPS) convergence, today announced it has acquired the assets, including intellectual property, and foreign subsidiaries of Sequence Design, the EDA leader in RTL Design for Power (DFP)™ solution. Sequence operations will be integrated under Apache’s global research and development, sales, support and marketing functions. Vic Kulkarni, President and CEO of Sequence Design, will assume the role of Senior Vice President and General Manager of RTL Business Unit in Apache. Terms of the transaction were not disclosed.

Through this acquisition, Apache expands power and noise product offerings from SoC, analog/mixed-signal, and package/PCB designs to the RTL where greater opportunity for power optimizations can be realized. The combination of Sequence’s technology and Apache’s power sign-off platforms raises the power-based solutions to the same level of importance as area and timing based tools.

“Sequence Design has established a solid reputation and customer base in RTL power analysis and reduction,” said Andrew Yang, CEO of Apache, “This acquisition reinforces Apache’s business and product strategy for complete offering of advanced power and noise integrity solutions for chip-package-system convergence.”

“Apache has demonstrated an impressive growth in the marketplace and established a critical mass of customer base, financial strength, and management experience. Our team looks forward to contributing to its continued success,” said Vic Kulkarni, President and CEO of Sequence.

Sequence Products:

PowerTheater, PowerArtist, Cool Products and Columbus will continue to be supported by Apache.

Apache Design SolutionsCPM, NSPICE, RedHawk, PakSI-E, PsiWinder, Sentinel, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc

Source:
http://www.apache-da.com/apache-da/Home/NewsandEvents/PressReleases/09.08.09.html
http://www.reuters.com/article/pressRelease/idUS225568+08-Sep-2009+BW20090908
http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=219700024

IEEE 1801: UPF achieves formal standardisation as IEEE-1801

The IEEE and the EDA-industry alliance Accellera
Shrenik Mehta, chairman of Accellera observes, "Industry acceptance of the IEEE 1801 standard power format can help optimize the energy consumption of future electronic systems by enabling engineers and tools to characterize and improve semiconductor power usage much earlier in the design cycle." announced today that the IEEE has approved a new standard, IEEE 1801, "Standard for Design and Verification of Low Power Integrated Circuits." The standard is also known as Unified Power Format (UPF) 2.0, and engineers in many chip-design teams worldwide already employ it to convey aspects of an IC design that are critical to low-power specifications from one tool to another throughout an electronic system design, analysis, verification and implementation flow.

EDA Blog: The IEEE has approved a new IEEE 1801 standard for Design and Verification of Low Power Integrated Circuits. The standard is also known as Unified Power Format (UPF) 2.0. UPF (first developed by Accellera) and is currently supported by multiple vendors and is in use worldwide. This is the first time that UPF has undergone an IEEE standardization effort. The IEEE 1801 standard provides portability of low-power design specifications that can be used with a variety of commercial products throughout an electronic system design, analysis, verification and implementation flow. Enhancements to UPF in the new standard include support for bias supplies (N-well, P-well, Deep-N-Well, and Deep-P-Well), greater flexibility and capabilities in specification of power states, and enhanced semantic capabilities for merged power domains.

References:
IEEE Standards Association
http://www.accellera.org/activities/p1801_upf/
http://www.accellera.org/join/roster/
http://standards.ieee.org/announcements/pr_ieee1801.html

EDA supporting UPF:

• Magma Design Automation
• Mentor Graphics
• Synopsys Inc.

Application engineers (EDN Blog)

Application engineers

Application engineers are the unsung heroes of EDA. They have to blend the technical skills of designers with the interpersonal skills of salespeople. Most AEs start out as design engineers (or software engineers for the embedded market). But not all design engineers make it as AEs, partially because, as I’m sure you’ve noticed, not all design engineers have good interpersonal skills! There’s also another problem, memorably described to me years ago by Devadas Varma: “they’ve only been in the restaurant before; now they’re in the kitchen they’re not so keen on what it takes to prepare the food.” Being an AE means cutting more corners than being a design engineer, and some people just don’t have that temperament. An AE usually has to produce a 95% solution quickly; a design engineer has to take whatever time it takes to produce a 100% solution.

AEs have a lot of options in their career path. As they become more senior and more experienced they have four main routes that they can take.

Read More - http://www.edn.com/blog/920000692/post/1110046111.html

Source: EDN